Claudio Bantaloukas <claudio.bantalou...@arm.com> writes:
> According to the aapcs64: If the argument is an 8-bit (...) precision
> Floating-point or short vector type and the NSRN is less than 8, then the
> argument is allocated to the least significant bits of register v[NSRN].
>
> gcc/
> * config/aarch64/aarch64.cc
> (aarch64_vfp_is_call_or_return_candidate): use fp registers to
> return svmfloat8_t parameters.
>
> gcc/testsuite/
> * gcc.target/aarch64/fp8_scalar_1.c:
LGTM, thanks. Pushed to trunk.
Richard
> ---
> gcc/config/aarch64/aarch64.cc | 3 ++-
> gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index f2b53475adb..0e2f9ef0ca1 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -22276,7 +22276,8 @@ aarch64_vfp_is_call_or_return_candidate (machine_mode
> mode,
>
> if ((!composite_p
> && (GET_MODE_CLASS (mode) == MODE_FLOAT
> - || GET_MODE_CLASS (mode) == MODE_DECIMAL_FLOAT))
> + || GET_MODE_CLASS (mode) == MODE_DECIMAL_FLOAT
> + || (type && TYPE_MAIN_VARIANT (type) == aarch64_mfp8_type_node)))
> || aarch64_short_vector_p (type, mode))
> {
> *count = 1;
> diff --git a/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c
> b/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c
> index 1bc2ac26b2a..61edf06401b 100644
> --- a/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c
> +++ b/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c
> @@ -7,10 +7,10 @@
>
> /*
> **stacktest1:
> +** umov w0, v0.b\[0\]
> ** sub sp, sp, #16
> -** and w0, w0, 255
> ** strb w0, \[sp, 15\]
> -** ldrb w0, \[sp, 15\]
> +** ldr b0, \[sp, 15\]
> ** add sp, sp, 16
> ** ret
> */
