On Fri, Nov 8, 2024 at 8:11 AM Claudio Bantaloukas
<claudio.bantalou...@arm.com> wrote:
>
>
> According to the aapcs64: If the argument is an 8-bit (...) precision
> Floating-point or short vector type and the NSRN is less than 8, then the
> argument is allocated to the least significant bits of register v[NSRN].
>
> gcc/
> * config/aarch64/aarch64.cc
> (aarch64_vfp_is_call_or_return_candidate): use fp registers to
> return svmfloat8_t parameters.
>
> gcc/testsuite/
> * gcc.target/aarch64/fp8_scalar_1.c:
This changed fp8_scalar_1.c's stacktest1 body but the generated code
there changed to be just:
sub sp, sp, #16
str b0, [sp, 15]
ldr b0, [sp, 15]
add sp, sp, 16
ret
Instead of having to require a move to the GPRs.
This code generation seems correct for what it is testing. Did
something else change the generated code after you made the change to
the testcase or was it still failing?
Thanks,
Andrew
> ---
> gcc/config/aarch64/aarch64.cc | 3 ++-
> gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
