No. It will need to change all patterns in vector.md. It's a nightmare. You should note I will refine vector.md in GCC-15, mixing theadvector things make me impossible to maintain RVV1.0.
juzhe.zh...@rivai.ai From: Andrew Pinski Date: 2024-01-03 11:19 To: juzhe.zh...@rivai.ai CC: jeffreyalaw; cooper.joshua; gcc-patches; Jim Wilson; palmer; andrew; philipp.tomsich; christoph.muellner; jinma; cooper.qu Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. On Tue, Jan 2, 2024 at 7:07 PM juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> wrote: > > We have no choice. You should know theadvector is totally unrelated with > RVV1.0 standard ISA. > > Adding `%^' which missing totally unrelated ISA makes no sens to me. No, it implements it in a different way. Basically all of the patterns which are supported get changed to be instead of "v*" becomes instead "%^v" and then you change riscv_print_operand_punct_valid_p to allow '^' and then you add '^' support to riscv_print_operand (like '~' is handled there). And the next patch adds a few more '%' to support printing different different strings based on XTheadVector or not. This is how almost all other targets handle this kind of things instead of hacking ASM_OUTPUT_OPCODE . Thanks, Andrew Pinski > > ________________________________ > juzhe.zh...@rivai.ai > > > From: Andrew Pinski > Date: 2024-01-03 10:54 > To: 钟居哲 > CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilson.gcc; palmer; andrew; > philipp.tomsich; Christoph Müllner; jinma; Cooper Qu > Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the > instructions of XTheadVector. > On Mon, Jan 1, 2024 at 2:59 PM 钟居哲 <juzhe.zh...@rivai.ai> wrote: > > > > This is Ok from my side. > > But before commit this patch, I think we need this patch first: > > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html > > > > I will be back to work so I will take a look at other patches today. > > > Note I hate it. It would be better if you use something like `%^' (see > `~` for an example of how that works) instead of hacking > riscv_asm_output_opcode really. In fact that is how other targets > implement this kind of things. > > Thanks, > Andrew PInski > > > ________________________________ > > juzhe.zh...@rivai.ai > > > > > > From: Jeff Law > > Date: 2024-01-01 01:43 > > To: Jun Sha (Joshua); gcc-patches > > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; > > juzhe.zhong; Jin Ma; Xianmiao Qu > > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions > > of XTheadVector. > > > > > > On 12/28/23 21:19, Jun Sha (Joshua) wrote: > > > This patch adds th. prefix to all XTheadVector instructions by > > > implementing new assembly output functions. We only check the > > > prefix is 'v', so that no extra attribute is needed. > > > > > > gcc/ChangeLog: > > > > > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode): > > > New function to add assembler insn code prefix/suffix. > > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. > > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise. > > > > > > Co-authored-by: Jin Ma <ji...@linux.alibaba.com> > > > Co-authored-by: Xianmiao Qu <cooper...@linux.alibaba.com> > > > Co-authored-by: Christoph Müllner <christoph.muell...@vrull.eu> > > > --- > > > gcc/config/riscv/riscv-protos.h | 1 + > > > gcc/config/riscv/riscv.cc | 14 ++++++++++++++ > > > gcc/config/riscv/riscv.h | 4 ++++ > > > .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 ++++++++++++ > > > 4 files changed, 31 insertions(+) > > > create mode 100644 > > > gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c > > > > > > diff --git a/gcc/config/riscv/riscv-protos.h > > > b/gcc/config/riscv/riscv-protos.h > > > index 31049ef7523..5ea54b45703 100644 > > > --- a/gcc/config/riscv/riscv-protos.h > > > +++ b/gcc/config/riscv/riscv-protos.h > > > @@ -102,6 +102,7 @@ struct riscv_address_info { > > > }; > > > > > > /* Routines implemented in riscv.cc. */ > > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const > > > char *p); > > > extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); > > > extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); > > > extern int riscv_float_const_rtx_index_for_fli (rtx); > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > > index 0d1cbc5cb5f..ea1d59d9cf2 100644 > > > --- a/gcc/config/riscv/riscv.cc > > > +++ b/gcc/config/riscv/riscv.cc > > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode) > > > return lmul; > > > } > > > > > > +/* Define ASM_OUTPUT_OPCODE to do anything special before > > > + emitting an opcode. */ > > > +const char * > > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p) > > > +{ > > > + /* We need to add th. prefix to all the xtheadvector > > > + insturctions here.*/ > > > + if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX && > > > + p[0] == 'v') > > > + fputs ("th.", asm_out_file); > > > + > > > + return p; > > Just a formatting nit. The GNU standards break lines before the > > operator, not after. So > > if (TARGET_XTHEADVECTOR > > && current_output_insn != NULL > > && p[0] == 'v') > > > > Note that current_output_insn is "extern rtx_insn *", so use NULL, not > > NULL_RTX. > > > > Neither of these nits require a new version for review. Just fix them. > > > > If Juzhe is fine with this, so am I. We can refine it if necessary later. > > > > jeff > > >
