On Wed, Aug 9, 2023 at 9:21 AM Hongtao Liu <crazy...@gmail.com> wrote: > > On Wed, Aug 9, 2023 at 3:55 AM Joseph Myers <jos...@codesourcery.com> wrote: > > > > Do you have any comments on the interaction of AVX10 with the > > micro-architecture levels defined in the ABI (and supported with > > glibc-hwcaps directories in glibc)? Given that the levels are cumulative, > > should we take it that any future levels will be ones supporting 512-bit > > vector width for AVX10 (because x86-64-v4 requires the current AVX512F, > > AVX512BW, AVX512CD, AVX512DQ and AVX512VL) - and so any future processors > > that only support 256-bit vector width will be considered to match the > > x86-64-v3 micro-architecture level but not any higher level? > This is actually something we really want to discuss in the community, > our proposal for x86-64-v5: AVX10.2-256(Implying AVX10.1-256) + APX. > One big reason is Intel E-core will only support AVX10 256-bit, if we > want to use x86-64-v5 accross server and client, it's better to > 256-bit default. + ABI and LLVM folked for this topic. > > > > -- > > Joseph S. Myers > > jos...@codesourcery.com > > > > -- > BR, > Hongtao
-- BR, Hongtao
