Do you have any comments on the interaction of AVX10 with the micro-architecture levels defined in the ABI (and supported with glibc-hwcaps directories in glibc)? Given that the levels are cumulative, should we take it that any future levels will be ones supporting 512-bit vector width for AVX10 (because x86-64-v4 requires the current AVX512F, AVX512BW, AVX512CD, AVX512DQ and AVX512VL) - and so any future processors that only support 256-bit vector width will be considered to match the x86-64-v3 micro-architecture level but not any higher level?
-- Joseph S. Myers jos...@codesourcery.com
