On 6/23/23 06:54, Li, Pan2 wrote:
Thanks Robine for the explanation, it is very clear to me. Totally agree below
parts and I think we can leave it to the maintainers of the RTL/Machine
Descriptions.
Now we could argue that combine's behavior should change here and an
insn without any alternatives is not actually available but that's not
a battle I'm willing to fight 😃
Pan
-----Original Message-----
From: Robin Dapp <rdapp....@gmail.com>
Sent: Thursday, June 22, 2023 10:31 PM
To: Li, Pan2 <pan2...@intel.com>; 钟居哲 <juzhe.zh...@rivai.ai>; gcc-patches
<gcc-patches@gcc.gnu.org>; palmer <pal...@dabbelt.com>; kito.cheng <kito.ch...@gmail.com>; Jeff
Law <jeffreya...@gmail.com>
Cc: rdapp....@gmail.com
Subject: Re: [PATCH] RISC-V: Split VF iterators for Zvfh(min).
Just curious about the combine pass you mentioned, not very sure my
understand is correct but it looks like the combine pass totally
ignore the iterator requirement?
It is sort of surprise to me as the combine pass may also need the
information of iterators.
combine tries to match instructions (with fitting modes of course).
It does not look at the insn constraints that reload/lra later can
use to switch between alternatives depending on the register situation
and other factors.
We e.g. have an instruction
(define_insn "bla"
(set (match_operand:VF 1 "=vd")
(match_operand:VF 2 "vr"))
...
and implicitly
[(set_attr "enabled" "true")]
This instruction gets multiplexed via the VF iterator into (among others)
(define_insn "bla"
(set (match_operand:VNx4HF 1 "=vd")
(match_operand:VNx4HF 2 "vr"))
...
[(set_attr "enabled" "true")]
When we set "enabled" to "false" via "fp_vector_disabled", we have:
(define_insn "bla"
(set (match_operand:VNx4HF 1 "=vd")
(match_operand:VNx4HF 2 "vr"))
...
[(set_attr "enabled" "false")]
This means the only available alternative is disabled but the insn
itself is still there, particularly for combine which does not look
into the constraints.
So in our case the iterator "allowed" the instruction (leading combine
to think it is available) and we later masked it out with "enabled = false".
Now we could argue that combine's behavior should change here and an
insn without any alternatives is not actually available but that's not
a battle I'm willing to fight :D
More importantly, at combine time we don't know which alternative will
match. In fact, you can run into cases where no alternative matches
until register allocation -- this was fairly common in the past as it
allowed for simpler machine descriptions. It fell out of favor in the
90s as more targets started using scheduling and we wanted to expose as
much of the final code as we could for the first scheduling pass.
Jeff
