Just curious about the combine pass you mentioned, not very sure my understand is correct but it looks like the combine pass totally ignore the iterator requirement?
It is sort of surprise to me as the combine pass may also need the information of iterators. Pan From: 钟居哲 <juzhe.zh...@rivai.ai> Sent: Thursday, June 22, 2023 9:37 PM To: rdapp.gcc <rdapp....@gmail.com>; gcc-patches <gcc-patches@gcc.gnu.org>; palmer <pal...@dabbelt.com>; kito.cheng <kito.ch...@gmail.com>; Li, Pan2 <pan2...@intel.com>; Jeff Law <jeffreya...@gmail.com> Cc: rdapp.gcc <rdapp....@gmail.com> Subject: Re: Re: [PATCH] RISC-V: Split VF iterators for Zvfh(min). Oh. I see. I think I am wrong. Sorry for that :). load/store are using 'V' iterators. This patch looks reasonable to me now. Thanks for catching this. ________________________________ juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: Robin Dapp<mailto:rdapp....@gmail.com> Date: 2023-06-22 21:32 To: 钟居哲<mailto:juzhe.zh...@rivai.ai>; gcc-patches<mailto:gcc-patches@gcc.gnu.org>; palmer<mailto:pal...@dabbelt.com>; kito.cheng<mailto:kito.ch...@gmail.com>; pan2.li<mailto:pan2...@intel.com>; Jeff Law<mailto:jeffreya...@gmail.com> CC: rdapp.gcc<mailto:rdapp....@gmail.com> Subject: Re: [PATCH] RISC-V: Split VF iterators for Zvfh(min). > I don't understand why it is necessary to bother "VF". "VF” should > not be changed since intrinsic stuff is quite stable and any > unreasonable changes are unacceptable. Ok, I hear your concern. My argument is: Currently our mechanism of disabling instructions is incorrect and if any of the VF instructions were to be created by combine, fwprop or other passes we'd potentially ICE in reload. The other option is to leave VF unchanged and duplicate all patterns for VHF. Those can have a TARGET_ZVFH then. > vle/vse/vluxei/vloxei/vsuxei/vsoxei/vlse/vsse. These are all V/VT and not VF? (apart from vlse which I adjusted) Regards Robin
