On Wed, Sep 23, 2020 at 09:28:33AM -0500, Qing Zhao wrote:
> > On Sep 22, 2020, at 5:37 PM, Segher Boessenkool
> > <seg...@kernel.crashing.org> wrote:
> >> which is very similar to the unspec_volatile case we're talking about.
> >
> > So just like volatile memory accesses, they have an (unknown) side
> > effect, which means they have to execute on the real machine as on the
> > abstract machine (wrt sequence points). All side effects have to happen
> > exactly as often as proscribed, and in the same order. Just like
> > volatile asm, too.
> Don’t quite understand the above, what do you mean by “they have to
> execute on the real machine as on the abstract machine”?
Exactly as described in the C standard.
> > (If you use "#" or "#smth" you can see those in the generated asm --
> > completely empty asm is helpfully (uh...) not printed.)
>
> Can you explain this in more details?
final.c... see
/* Output the insn using them. */
if (string[0])
{
(it doesn't output anything if an asm template is the empty string!)
> > Even then, x[] could be optimised away completely (with whole program
> > optimisation, or something). The only way to really prevent the
> > compiler from optimising memory accesses is to make it not see the
> > details (with an asm or an unspec, for example).
> You mean with a asm volatile (“” “memory”)?
No, I meant doing the memory access from asm. The only way to get
exactly the machine instructions you want is to write it in assembler
(inline assembler usually can work, too).
> >> The above is conservatively correct. But not all passes do it.
> >> E.g. combine does have a similar approach:
> >>
> >> /* If INSN contains volatile references (specifically volatile MEMs),
> >> we cannot combine across any other volatile references.
> >
> > And this is correct, and the *minimum* to do even (this could change the
> > order of the side effects, depending how combine places the resulting
> > insns in I2 and I3).
>
> Please clarify what “L2 and L3” are?
I2 and I3. Combine name the insns it combines I0, I1, I2, and I3, and
writes the new insns it generates to the places of I2 and I3. (In both
cases all of the lower numbered insns can be omitted, e.g. combine I2,
I3 into a new I3. That is the general gist; there is some other stuff,
like, erm, "other_insn" :-) .)
Segher
