Hi! On Fri, Sep 18, 2020 at 03:31:12PM -0500, Qing Zhao wrote: > Let me know your opinion: > > A. Will not provide default definition in middle end to generate the zeroing > insn for selected registers. Move the generation work all to target; X86 > implementation will be provided; > > OR: > > B. Will provide a default definition in middle end to generate the zeroing > insn for selected registers. Then need to add a new target hook > “ZERO_CALL_USED_REGNO_P(REGNO, GPR_ONLY)”, same as A, X86 implementation will > be provided in my patch.
Is this just to make the xor thing work? i386 has a peephole to transform the mov to a xor for this (and the backend could just handle it in its mov<M> patterns, maybe a peephole was easier for i386, no idea). Segher
