> On Sep 18, 2020, at 5:51 PM, Segher Boessenkool <seg...@kernel.crashing.org> 
> wrote:
> 
> Hi!
> 
> On Fri, Sep 18, 2020 at 03:31:12PM -0500, Qing Zhao wrote:
>> Let me know your opinion:
>> 
>> A.  Will not provide default definition in middle end to generate the 
>> zeroing insn for selected registers.  Move the generation work all to 
>> target; X86 implementation will be provided;
>> 
>> OR:
>> 
>> B.  Will provide a default definition in middle end to generate the zeroing 
>> insn for selected registers. Then need to add a new target hook 
>> “ZERO_CALL_USED_REGNO_P(REGNO, GPR_ONLY)”, same as A, X86 implementation 
>> will be provided in my patch. 
> 
> Is this just to make the xor thing work?  i386 has a peephole to
> transform the mov to a xor for this (and the backend could just handle
> it in its mov<M> patterns, maybe a peephole was easier for i386, no
> idea).

You mean what’s the purpose of the new target hook 
“ZERO_CALL_USED_REGNO_P(REGNO, GPR_ONLY)?

The purpose of this new target hook is for the target to delete some of the 
call_used registers that should not be zeroed, for example, the stack registers 
in X86. (St0-st7). 
For other platforms, there might be other call_used registers that should not 
be zeroed. 

Qing

> 
> 
> Segher

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