Hi Roman, Roman Zhuykov <zhr...@ispras.ru> writes:
> This patch is stage1 material, right? Yes >> >>> +(define_insn "*doloop_end" >>> + [(parallel [(set (pc) >>> + (if_then_else >>> + (ne (reg:SI LR_REGNUM) (const_int 1)) >>> + (label_ref (match_operand 0 "" "")) >>> + (pc))) >>> + (set (reg:SI LR_REGNUM) >>> + (plus:SI (reg:SI LR_REGNUM) (const_int -1)))])] >>> + "TARGET_32BIT && TARGET_HAVE_LOB && !flag_modulo_sched" >>> + "le\tlr, %l0") > I'm not an expert in .md files, but having that "!flag_modulo_sched" > condition seems wrong to me. What was the issue on SMS side to add > that? With this patch the first insn of the low loop overhead 'doloop_begin' is expanded by 'doloop_modify' in loop-doloop.c. The same does not happen with SMS. My understanding is that to have it working in that case too the machine dependent reorg pass should add it later. Am I correct on this? Thanks Andrea
