On 20 Oct 08:20, Shalnov, Sergey wrote: > I can't propose general solution since TARGET_PREFER256 is AVX512 specific. > Sorry for misunderstanding. Okay than. I've checked in your patch into main trunk, thanks!
-- K > Sergey > > -----Original Message----- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On > Behalf Of Kirill Yukhin > Sent: Wednesday, October 18, 2017 8:10 PM > To: Shalnov, Sergey <sergey.shal...@intel.com> > Cc: Jakub Jelinek <ja...@redhat.com>; 'gcc-patches@gcc.gnu.org' > <gcc-patches@gcc.gnu.org>; 'ubiz...@gmail.com' <ubiz...@gmail.com>; > Senkevich, Andrew <andrew.senkev...@intel.com>; Ivchenko, Alexander > <alexander.ivche...@intel.com>; Peryt, Sebastian <sebastian.pe...@intel.com> > Subject: Re: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in > Intel AVX512 configuration > > Hello Sergey, > On 06 Oct 14:20, Shalnov, Sergey wrote: > > Jakub, > > I completely agree with you. I fixed the patch. > > Currently, TARGET_PREFER256 will work on architectures with 512VL. It will > > not work otherwise. > > > > I will try to find better solution for this. I think I need to look > > into register classes to configure available registers for 512F and 512VL > > in case of TARGET_PREFER_AVX256. > Probably I am missing the point, but IMHO think register classes are loosely > connected to preferred modes of operations. > > > I would propose to merge this patch as temporal solution. > Why not to implement generic solution right now? > I don't think're in hurry here to push temporal solution unless we have some > reasoning. > > I see only few mentions of TARGET_PREFER_AVX256 in i386.[c|md] and nothing > looks suspicious to me. > > > > > Sergey > > -- > Thanks, K
