Uros, Is this patch (second one which fixed in the way as Jakub proposed) ok for the trunk? Could you please merge it? Sergey
-----Original Message----- From: Shalnov, Sergey Sent: Friday, October 6, 2017 4:20 PM To: Jakub Jelinek <ja...@redhat.com> Cc: 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>; 'ubiz...@gmail.com' <ubiz...@gmail.com>; 'kirill.yuk...@gmail.com' <kirill.yuk...@gmail.com>; Senkevich, Andrew <andrew.senkev...@intel.com>; Ivchenko, Alexander <alexander.ivche...@intel.com>; Peryt, Sebastian <sebastian.pe...@intel.com> Subject: RE: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration Jakub, I completely agree with you. I fixed the patch. Currently, TARGET_PREFER256 will work on architectures with 512VL. It will not work otherwise. I will try to find better solution for this. I think I need to look into register classes to configure available registers for 512F and 512VL in case of TARGET_PREFER_AVX256. I would propose to merge this patch as temporal solution. Sergey -----Original Message----- From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On Behalf Of Jakub Jelinek Sent: Friday, October 6, 2017 11:58 AM To: Shalnov, Sergey <sergey.shal...@intel.com> Cc: 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>; 'ubiz...@gmail.com' <ubiz...@gmail.com>; 'kirill.yuk...@gmail.com' <kirill.yuk...@gmail.com>; Senkevich, Andrew <andrew.senkev...@intel.com>; Ivchenko, Alexander <alexander.ivche...@intel.com>; Peryt, Sebastian <sebastian.pe...@intel.com> Subject: Re: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration On Fri, Oct 06, 2017 at 09:33:21AM +0000, Shalnov, Sergey wrote: > Hi, > GCC uses full 512-bit register in case of moving SF/DF value between two > registers. > The patch avoid 512-bit register usage if "-mprefer-avx256" option used. > > 2017-10-06 Sergey Shalnov <sergey.shal...@intel.com> > > gcc/ > * config/i386/i386.md(*movsf_internal, *movdf_internal): > Avoid 512-bit AVX modes for TARGET_PREFER_AVX256. > From b96e657153b9aea24ff002e7e156ba12b2d443b5 Mon Sep 17 00:00:00 2001 From: Sergey Shalnov <sergey.shal...@intel.com> Date: Fri, 6 Oct 2017 10:45:40 +0300 Subject: [PATCH 1/1] Avoid 512-bit mode MOV for prefer-avx256 option --- gcc/config/i386/i386.md | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 99497a9..a6d7cca 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3564,8 +3564,9 @@ /* movaps is one byte shorter for non-AVX targets. */ (eq_attr "alternative" "13,17") - (cond [(ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand")) + (cond [(and (not (match_test "TARGET_PREFER_AVX256")) + (ior (match_operand 0 "ext_sse_reg_operand") + (match_operand 1 "ext_sse_reg_operand"))) (const_string "V8DF") (ior (not (match_test "TARGET_SSE2")) (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) How does that work with -mprefer-avx256 -mavx512f -mno-avx512vl? The constraints in these alternatives use v, and [SD]Fmode are included in VALID_AVX512F_SCALAR_MODE and thus you can get e.g. %?mm23 among the operands. EVEX encoded VMOVAPD or VMOVAPS is AVX512F cpuid only with 512-bit operands, with 128-bit/256-bit it is AVX512VL + AVX512F. So, in both of the spots you've changed in this patch, but also in the spots you've changed earlier, you need to use TARGET_PREFER_AVX256 && TARGET_AVX512VL rather than just TARGET_PREFER_AVX256, because without TARGET_AVX512VL it is not a matter of preferring it, but a must. Unless we disable %xmm16+ registers for TARGET_PREFER_AVX256 && !TARGET_AVX512VL code, but that would be weird: an optimization preference would e.g. break people using %xmm16+ register variables etc. @@ -3739,8 +3740,9 @@ better to maintain the whole registers in single format to avoid problems on using packed logical operations. */ (eq_attr "alternative" "6") - (cond [(ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand")) + (cond [(and (not (match_test "TARGET_PREFER_AVX256")) + (ior (match_operand 0 "ext_sse_reg_operand") + (match_operand 1 "ext_sse_reg_operand"))) (const_string "V16SF") (ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY") (match_test "TARGET_SSE_SPLIT_REGS")) -- 1.8.3.1 Jakub
