[PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration

[Shalnov, Sergey]

Hi,
GCC uses full 512-bit register in case of moving SF/DF value between two 
registers.
The patch avoid 512-bit register usage if "-mprefer-avx256" option used.

2017-10-06  Sergey Shalnov  <sergey.shal...@intel.com>

gcc/
        * config/i386/i386.md(*movsf_internal, *movdf_internal):
        Avoid 512-bit AVX modes for TARGET_PREFER_AVX256.

0002-Avoid-512-bit-mode-MOV-for-prefer-avx256-option.patch
Description: 0002-Avoid-512-bit-mode-MOV-for-prefer-avx256-option.patch