On 30 August 2016 at 18:45, Tamar Christina <tamar.christ...@arm.com> wrote: > > > On 30/08/16 17:11, Christophe Lyon wrote: >> >> On 18 August 2016 at 11:15, Tamar Christina <tamar.christ...@arm.com> >> wrote: >>> >>> Hi all, >>> >>> This fixes a bug in the vector load functions in which they load the >>> vector in the wrong order for big endian systems. This patch flips the >>> order conditionally in the vec_concats. >>> >>> No testcase given because plenty of existing tests for vld functions. >>> Ran regression tests on aarch64_be-none-elf and aarch64-none-elf. >>> Vldx tests now pass on aarch64_be-none-elf and no regressions on both. >>> >> Before your patch, I can see aarch64/vldN_1.c and >> aarch64/advsimd-intrinsics/vldX_lane.c failing. >> >> Do you know why aarch64/advsimd-intrinsics/vldX.c and vldX_dup >> are not failing? > > That's weird, on my clean build and our nightlies I see > > aarch64/advsimd-intrinsics/vldX.c, aarch64/advsimd-intrinsics/vtbX.c and > aarch64/vldN_1.c failing but > aarch64/advsimd-intrinsics/vldX_lane.c is passing. > > I don't know why the vldX_lane was passing, but I'll look into the > discrepancy. >
Hmmm I must have looked at the wrong place :( Your patch does fix vtbX, vldX and vldN_1 tests. Sorry for the noise. Christophe > Cheers, > Tamar > >> Thanks >> Christophe >> >>> Ok for trunk? >>> >>> I do not have commit rights so if ok can someone apply it for me? >>> >>> Thanks, >>> Tamar >>> >>> gcc/ >>> 2016-08-16 Tamar Christina <tamar.christ...@arm.com> >>> >>> * gcc/config/aarch64/aarch64-simd.md >>> (aarch64_ld2<mode>_dreg_le): New. >>> (aarch64_ld2<mode>_dreg_be): New. >>> (aarch64_ld2<mode>_dreg): Removed. >>> (aarch64_ld3<mode>_dreg_le): New. >>> (aarch64_ld3<mode>_dreg_be): New. >>> (aarch64_ld3<mode>_dreg): Removed. >>> (aarch64_ld4<mode>_dreg_le): New. >>> (aarch64_ld4<mode>_dreg_be): New. >>> (aarch64_ld4<mode>_dreg): Removed. >>> (aarch64_ld<VSTRUCT:nregs><VDC:mode>): Wrapper around _le, _be. > >
