On 18 August 2016 at 11:15, Tamar Christina <tamar.christ...@arm.com> wrote: > Hi all, > > This fixes a bug in the vector load functions in which they load the > vector in the wrong order for big endian systems. This patch flips the > order conditionally in the vec_concats. > > No testcase given because plenty of existing tests for vld functions. > Ran regression tests on aarch64_be-none-elf and aarch64-none-elf. > Vldx tests now pass on aarch64_be-none-elf and no regressions on both. > Before your patch, I can see aarch64/vldN_1.c and aarch64/advsimd-intrinsics/vldX_lane.c failing.
Do you know why aarch64/advsimd-intrinsics/vldX.c and vldX_dup are not failing? Thanks Christophe > Ok for trunk? > > I do not have commit rights so if ok can someone apply it for me? > > Thanks, > Tamar > > gcc/ > 2016-08-16 Tamar Christina <tamar.christ...@arm.com> > > * gcc/config/aarch64/aarch64-simd.md > (aarch64_ld2<mode>_dreg_le): New. > (aarch64_ld2<mode>_dreg_be): New. > (aarch64_ld2<mode>_dreg): Removed. > (aarch64_ld3<mode>_dreg_le): New. > (aarch64_ld3<mode>_dreg_be): New. > (aarch64_ld3<mode>_dreg): Removed. > (aarch64_ld4<mode>_dreg_le): New. > (aarch64_ld4<mode>_dreg_be): New. > (aarch64_ld4<mode>_dreg): Removed. > (aarch64_ld<VSTRUCT:nregs><VDC:mode>): Wrapper around _le, _be.
