On 13/05/16 16:16, James Greenhalgh wrote:
On Wed, May 11, 2016 at 03:24:00PM +0200, Christophe Lyon wrote:
2016-05-02 Christophe Lyon <christophe.l...@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (result):
Add poly64x1_t and poly64x2_t cases if supported.
* gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
(buffer, buffer_pad, buffer_dup, buffer_dup_pad): Likewise.
* gcc.target/aarch64/advsimd-intrinsics/p64_p128.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: New file.
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
@@ -0,0 +1,665 @@
+/* This file contains tests for all the *p64 intrinsics, except for
+ vreinterpret which have their own testcase. */
+
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results: vbsl. */
+VECT_VAR_DECL(vbsl_expected,poly,64,1) [] = { 0xfffffff1 };
+VECT_VAR_DECL(vbsl_expected,poly,64,2) [] = { 0xfffffff1,
+ 0xfffffff1 };
+
+/* Expected results: vceq. */
+VECT_VAR_DECL(vceq_expected,uint,64,1) [] = { 0x0 };
vceqq_p64
vceqz_p64
vceqzq_p64
vtst_p64
vtstq_p64
are missing, but will not be trivial to add. Could you raise a bug report
(or fix it if you like :-) )?
This is OK without a fix for those intrinsics with a suitable bug report
opened.
That's ok by me too.
Thanks,
Kyrill
Thanks,
James
