Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

[Jiong Wang]

On 12/05/16 13:56, Christophe Lyon wrote:
On 12 May 2016 at 10:45, Jiong Wang <jiong.w...@foss.arm.com> wrote:

On 11/05/16 14:23, Christophe Lyon wrote:
2016-05-02  Christophe Lyon  <christophe.l...@linaro.org>

         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc:
New.
         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c:
New.
         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c:
New.
         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c:
New.
         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c:
New.
         * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c:
New.

Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
new file mode 100644
index 0000000..5f492d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
+                                              0xc1600000, 0xc1500000 };
+
+#define INSN vrnd
+#define TEST_MSG "VRND"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
new file mode 100644
index 0000000..629240d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
@@ -0,0 +1,43 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1 (NAME)
+
+void FNNAME (INSN) (void)
+{
+  /* vector_res = vrndX (vector), then store the result.  */
+#define TEST_VRND2(INSN, Q, T1, T2, W, N)                              \
+  VECT_VAR (vector_res, T1, W, N) =                                    \
+    INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));                   \
+    vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),                    \
+                      VECT_VAR (vector_res, T1, W, N))
+
+  /* Two auxliary macros are necessary to expand INSN.  */
+#define TEST_VRND1(INSN, Q, T1, T2, W, N)      \
+  TEST_VRND2 (INSN, Q, T1, T2, W, N)
+
+#define TEST_VRND(Q, T1, T2, W, N)             \
+  TEST_VRND1 (INSN, Q, T1, T2, W, N)
+
+  DECL_VARIABLE (vector, float, 32, 2);
+  DECL_VARIABLE (vector, float, 32, 4);
+
+  DECL_VARIABLE (vector_res, float, 32, 2);
+  DECL_VARIABLE (vector_res, float, 32, 4);
+
+  clean_results ();
+
+  VLOAD (vector, buffer, , float, f, 32, 2);
+  VLOAD (vector, buffer, q, float, f, 32, 4);
+
+  TEST_VRND ( , float, f, 32, 2);
+  TEST_VRND (q, float, f, 32, 4);
+
+  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
+  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int
+main (void)
+{
+  FNNAME (INSN) ();
+  return 0;
+}

Hi Christophe,

   I have a question on how test inputs are selected?

   For example vrndm is round to integral, towards minus infinity while vrnda
is to nearest with ties to even, has these differences been tested?

Hi Jiong,

For this particular case, no, I didn't specifically chose input values to check
these differences.

This can be done as a follow-up?

I think it's fine as this patch series itself is anyway a step forward 
on making sure all intrinsics are tested.

Thanks.

Regards,
Jiong