Following on from the two patches I've just posted, this one makes
config/i386/*.md use match_test for .md attributes. Tested as
described here:
http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01182.html
OK to install?
Richard
gcc/
* config/i386/i386.md: Use (match_test ...) for attribute tests.
* config/i386/mmx.md: Likewise.
* config/i386/sse.md: Likewise.
Index: gcc/config/i386/i386.md
===================================================================
--- gcc/config/i386/i386.md 2011-08-13 11:06:03.000000000 +0100
+++ gcc/config/i386/i386.md 2011-08-13 11:06:08.000000000 +0100
@@ -478,18 +478,16 @@ (define_attr "prefix_0f" ""
;; Set when REX opcode prefix is used.
(define_attr "prefix_rex" ""
- (cond [(eq (symbol_ref "TARGET_64BIT") (const_int 0))
+ (cond [(not (match_test "TARGET_64BIT"))
(const_int 0)
(and (eq_attr "mode" "DI")
(and (eq_attr "type" "!push,pop,call,callv,leave,ibr")
(eq_attr "unit" "!mmx")))
(const_int 1)
(and (eq_attr "mode" "QI")
- (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
- (const_int 0)))
+ (match_test "x86_extended_QIreg_mentioned_p (insn)"))
(const_int 1)
- (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
- (const_int 0))
+ (match_test "x86_extended_reg_mentioned_p (insn)")
(const_int 1)
(and (eq_attr "type" "imovx")
(match_operand:QI 1 "ext_QIreg_operand" ""))
@@ -539,7 +537,7 @@ (define_attr "modrm" ""
(eq_attr "unit" "i387")
(const_int 0)
(and (eq_attr "type" "incdec")
- (and (eq (symbol_ref "TARGET_64BIT") (const_int 0))
+ (and (not (match_test "TARGET_64BIT"))
(ior (match_operand:SI 1 "register_operand" "")
(match_operand:HI 1 "register_operand" ""))))
(const_int 0)
@@ -585,7 +583,7 @@ (define_attr "length" ""
(attr "length_address")))
(ior (eq_attr "prefix" "vex")
(and (eq_attr "prefix" "maybe_vex")
- (ne (symbol_ref "TARGET_AVX") (const_int 0))))
+ (match_test "TARGET_AVX")))
(plus (attr "length_vex")
(plus (attr "length_immediate")
(plus (attr "modrm")
@@ -1911,16 +1909,13 @@ (define_insn "*movti_internal_rex64"
(set (attr "mode")
(cond [(eq_attr "alternative" "2,3")
(if_then_else
- (ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0))
+ (match_test "optimize_function_for_size_p (cfun)")
(const_string "V4SF")
(const_string "TI"))
(eq_attr "alternative" "4")
(if_then_else
- (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0))
- (ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SSE_TYPELESS_STORES")
+ (match_test "optimize_function_for_size_p (cfun)"))
(const_string "V4SF")
(const_string "TI"))]
(const_string "DI")))])
@@ -1969,13 +1964,11 @@ (define_insn "*movti_internal_sse"
[(set_attr "type" "sselog1,ssemov,ssemov")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (cond [(ior (eq (symbol_ref "TARGET_SSE2") (const_int 0))
- (ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0)))
+ (cond [(ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
(const_string "V4SF")
(and (eq_attr "alternative" "2")
- (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0)))
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
(const_string "V4SF")]
(const_string "TI")))])
@@ -2289,11 +2282,11 @@ (define_insn "*movsi_internal"
(const_string "DI")
(eq_attr "alternative" "6,7")
(if_then_else
- (eq (symbol_ref "TARGET_SSE2") (const_int 0))
+ (not (match_test "TARGET_SSE2"))
(const_string "V4SF")
(const_string "TI"))
(and (eq_attr "alternative" "8,9,10,11")
- (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
+ (not (match_test "TARGET_SSE2")))
(const_string "SF")
]
(const_string "SI")))])
@@ -2317,20 +2310,16 @@ (define_insn "*movhi_internal"
}
}
[(set (attr "type")
- (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0))
+ (cond [(match_test "optimize_function_for_size_p (cfun)")
(const_string "imov")
(and (eq_attr "alternative" "0")
- (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
- (const_int 0))
- (eq (symbol_ref "TARGET_HIMODE_MATH")
- (const_int 0))))
+ (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
+ (not (match_test "TARGET_HIMODE_MATH"))))
(const_string "imov")
(and (eq_attr "alternative" "1,2")
(match_operand:HI 1 "aligned_operand" ""))
(const_string "imov")
- (and (ne (symbol_ref "TARGET_MOVX")
- (const_int 0))
+ (and (match_test "TARGET_MOVX")
(eq_attr "alternative" "0,2"))
(const_string "imovx")
]
@@ -2342,10 +2331,8 @@ (define_insn "*movhi_internal"
(match_operand:HI 1 "aligned_operand" ""))
(const_string "SI")
(and (eq_attr "alternative" "0")
- (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
- (const_int 0))
- (eq (symbol_ref "TARGET_HIMODE_MATH")
- (const_int 0))))
+ (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
+ (not (match_test "TARGET_HIMODE_MATH"))))
(const_string "SI")
]
(const_string "HI")))])
@@ -2381,19 +2368,15 @@ (define_insn "*movqi_internal"
(cond [(and (eq_attr "alternative" "5")
(not (match_operand:QI 1 "aligned_operand" "")))
(const_string "imovx")
- (ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0))
+ (match_test "optimize_function_for_size_p (cfun)")
(const_string "imov")
(and (eq_attr "alternative" "3")
- (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
- (const_int 0))
- (eq (symbol_ref "TARGET_QIMODE_MATH")
- (const_int 0))))
+ (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
+ (not (match_test "TARGET_QIMODE_MATH"))))
(const_string "imov")
(eq_attr "alternative" "3,5")
(const_string "imovx")
- (and (ne (symbol_ref "TARGET_MOVX")
- (const_int 0))
+ (and (match_test "TARGET_MOVX")
(eq_attr "alternative" "2"))
(const_string "imovx")
]
@@ -2407,20 +2390,15 @@ (define_insn "*movqi_internal"
(const_string "SI")
(and (eq_attr "type" "imov")
(and (eq_attr "alternative" "0,1")
- (and (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
- (const_int 0))
- (and (eq (symbol_ref "optimize_function_for_size_p
(cfun)")
- (const_int 0))
- (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
- (const_int 0))))))
+ (and (match_test "TARGET_PARTIAL_REG_DEPENDENCY")
+ (and (not (match_test "optimize_function_for_size_p
(cfun)"))
+ (not (match_test
"TARGET_PARTIAL_REG_STALL"))))))
(const_string "SI")
;; Avoid partial register stalls when not using QImode arithmetic
(and (eq_attr "type" "imov")
(and (eq_attr "alternative" "0,1")
- (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
- (const_int 0))
- (eq (symbol_ref "TARGET_QIMODE_MATH")
- (const_int 0)))))
+ (and (match_test "TARGET_PARTIAL_REG_STALL")
+ (not (match_test "TARGET_QIMODE_MATH")))))
(const_string "SI")
]
(const_string "QI")))])
@@ -2560,8 +2538,7 @@ (define_insn "*movqi_extv_1_rex64"
}
[(set (attr "type")
(if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
- (ne (symbol_ref "TARGET_MOVX")
- (const_int 0)))
+ (match_test "TARGET_MOVX"))
(const_string "imovx")
(const_string "imov")))
(set (attr "mode")
@@ -2587,8 +2564,7 @@ (define_insn "*movqi_extv_1"
[(set (attr "type")
(if_then_else (and (match_operand:QI 0 "register_operand" "")
(ior (not (match_operand:QI 0 "QIreg_operand" ""))
- (ne (symbol_ref "TARGET_MOVX")
- (const_int 0))))
+ (match_test "TARGET_MOVX")))
(const_string "imovx")
(const_string "imov")))
(set (attr "mode")
@@ -2624,8 +2600,7 @@ (define_insn "*movqi_extzv_2_rex64"
}
[(set (attr "type")
(if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
- (ne (symbol_ref "TARGET_MOVX")
- (const_int 0)))
+ (match_test "TARGET_MOVX"))
(const_string "imovx")
(const_string "imov")))
(set (attr "mode")
@@ -2652,8 +2627,7 @@ (define_insn "*movqi_extzv_2"
[(set (attr "type")
(if_then_else (and (match_operand:QI 0 "register_operand" "")
(ior (not (match_operand:QI 0 "QIreg_operand" ""))
- (ne (symbol_ref "TARGET_MOVX")
- (const_int 0))))
+ (match_test "TARGET_MOVX")))
(const_string "imovx")
(const_string "imov")))
(set (attr "mode")
@@ -2917,16 +2891,13 @@ (define_insn "*movtf_internal"
(set (attr "mode")
(cond [(eq_attr "alternative" "0,2")
(if_then_else
- (ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0))
+ (match_test "optimize_function_for_size_p (cfun)")
(const_string "V4SF")
(const_string "TI"))
(eq_attr "alternative" "1")
(if_then_else
- (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0))
- (ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SSE_TYPELESS_STORES")
+ (match_test "optimize_function_for_size_p (cfun)"))
(const_string "V4SF")
(const_string "TI"))]
(const_string "DI")))])
@@ -3064,11 +3035,9 @@ (define_insn "*movdf_internal_rex64"
/* xorps is one byte shorter. */
(eq_attr "alternative" "7")
- (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0))
+ (cond [(match_test "optimize_function_for_size_p (cfun)")
(const_string "V4SF")
- (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
- (const_int 0))
+ (match_test "TARGET_SSE_LOAD0_BY_PXOR")
(const_string "TI")
]
(const_string "V2DF"))
@@ -3080,11 +3049,9 @@ (define_insn "*movdf_internal_rex64"
movaps encodes one byte shorter. */
(eq_attr "alternative" "8")
(cond
- [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0))
+ [(match_test "optimize_function_for_size_p (cfun)")
(const_string "V4SF")
- (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
- (const_int 0))
+ (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
(const_string "V2DF")
]
(const_string "DF"))
@@ -3093,8 +3060,7 @@ (define_insn "*movdf_internal_rex64"
of register. */
(eq_attr "alternative" "9")
(if_then_else
- (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
- (const_int 0))
+ (match_test "TARGET_SSE_SPLIT_REGS")
(const_string "V1DF")
(const_string "DF"))
]
@@ -3180,7 +3146,7 @@ (define_insn "*movdf_internal"
(const_string "SI")
/* For SSE1, we have many fewer alternatives. */
- (eq (symbol_ref "TARGET_SSE2") (const_int 0))
+ (not (match_test "TARGET_SSE2"))
(if_then_else
(eq_attr "alternative" "5,6")
(const_string "V4SF")
@@ -3188,11 +3154,9 @@ (define_insn "*movdf_internal"
/* xorps is one byte shorter. */
(eq_attr "alternative" "5")
- (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0))
+ (cond [(match_test "optimize_function_for_size_p (cfun)")
(const_string "V4SF")
- (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
- (const_int 0))
+ (match_test "TARGET_SSE_LOAD0_BY_PXOR")
(const_string "TI")
]
(const_string "V2DF"))
@@ -3204,11 +3168,9 @@ (define_insn "*movdf_internal"
movaps encodes one byte shorter. */
(eq_attr "alternative" "6")
(cond
- [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0))
+ [(match_test "optimize_function_for_size_p (cfun)")
(const_string "V4SF")
- (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
- (const_int 0))
+ (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
(const_string "V2DF")
]
(const_string "DF"))
@@ -3217,8 +3179,7 @@ (define_insn "*movdf_internal"
of register. */
(eq_attr "alternative" "7")
(if_then_else
- (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
- (const_int 0))
+ (match_test "TARGET_SSE_SPLIT_REGS")
(const_string "V1DF")
(const_string "DF"))
]
@@ -3293,12 +3254,9 @@ (define_insn "*movsf_internal"
(const_string "SI")
(eq_attr "alternative" "5")
(if_then_else
- (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
- (const_int 0))
- (ne (symbol_ref "TARGET_SSE2")
- (const_int 0)))
- (eq (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0)))
+ (and (and (match_test "TARGET_SSE_LOAD0_BY_PXOR")
+ (match_test "TARGET_SSE2"))
+ (not (match_test "optimize_function_for_size_p
(cfun)")))
(const_string "TI")
(const_string "V4SF"))
/* For architectures resolving dependencies on
@@ -3313,10 +3271,8 @@ (define_insn "*movsf_internal"
to avoid problems on using packed logical operations. */
(eq_attr "alternative" "6")
(if_then_else
- (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
- (const_int 0))
- (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
- (const_int 0)))
+ (ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
+ (match_test "TARGET_SSE_SPLIT_REGS"))
(const_string "V4SF")
(const_string "SF"))
(eq_attr "alternative" "11")
@@ -4931,7 +4887,7 @@ (define_insn "*float<SWI48x:mode><MODEF:
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "prefix" "maybe_vex")
- (ne (symbol_ref "<SWI48x:MODE>mode == DImode") (const_int 0)))
+ (match_test "<SWI48x:MODE>mode == DImode"))
(const_string "1")
(const_string "*")))
(set_attr "unit" "i387,*,*")
@@ -4956,7 +4912,7 @@ (define_insn "*float<SWI48x:mode><MODEF:
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "prefix" "maybe_vex")
- (ne (symbol_ref "<SWI48x:MODE>mode == DImode") (const_int 0)))
+ (match_test "<SWI48x:MODE>mode == DImode"))
(const_string "1")
(const_string "*")))
(set_attr "athlon_decode" "*,direct")
@@ -5151,7 +5107,7 @@ (define_insn "*float<SWI48x:mode><MODEF:
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "prefix" "maybe_vex")
- (ne (symbol_ref "<SWI48x:MODE>mode == DImode") (const_int 0)))
+ (match_test "<SWI48x:MODE>mode == DImode"))
(const_string "1")
(const_string "*")))
(set_attr "athlon_decode" "double,direct")
@@ -5186,7 +5142,7 @@ (define_insn "*float<SWI48x:mode><MODEF:
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "prefix" "maybe_vex")
- (ne (symbol_ref "<SWI48x:MODE>mode == DImode") (const_int 0)))
+ (match_test "<SWI48x:MODE>mode == DImode"))
(const_string "1")
(const_string "*")))
(set_attr "athlon_decode" "direct")
@@ -7718,7 +7674,7 @@ (define_insn "*anddi_1"
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
- (and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
+ (and (match_test "INTVAL (operands[2]) == 0xff")
(match_operand 1 "ext_QIreg_operand" "")))
(const_string "1")
(const_string "*")))
@@ -7762,7 +7718,7 @@ (define_insn "*andsi_1"
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
- (and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
+ (and (match_test "INTVAL (operands[2]) == 0xff")
(match_operand 1 "ext_QIreg_operand" "")))
(const_string "1")
(const_string "*")))
@@ -9084,8 +9040,7 @@ (define_insn "*ashl<mode>3_1"
[(set (attr "type")
(cond [(eq_attr "alternative" "1")
(const_string "lea")
- (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
+ (and (and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
@@ -9096,8 +9051,8 @@ (define_insn "*ashl<mode>3_1"
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 ||
optimize_function_for_size_p (cfun)")
- (const_int 0)))))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p
(cfun)")))))
(const_string "0")
(const_string "*")))
(set_attr "mode" "<MODE>")])
@@ -9130,8 +9085,7 @@ (define_insn "*ashlsi3_1_zext"
[(set (attr "type")
(cond [(eq_attr "alternative" "1")
(const_string "lea")
- (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
+ (and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 2 "const1_operand" ""))
(const_string "alu")
]
@@ -9141,8 +9095,8 @@ (define_insn "*ashlsi3_1_zext"
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 ||
optimize_function_for_size_p (cfun)")
- (const_int 0)))))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p
(cfun)")))))
(const_string "0")
(const_string "*")))
(set_attr "mode" "SI")])
@@ -9170,8 +9124,7 @@ (define_insn "*ashlhi3_1"
}
}
[(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
+ (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
@@ -9182,8 +9135,8 @@ (define_insn "*ashlhi3_1"
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 ||
optimize_function_for_size_p (cfun)")
- (const_int 0)))))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p
(cfun)")))))
(const_string "0")
(const_string "*")))
(set_attr "mode" "HI")])
@@ -9216,8 +9169,7 @@ (define_insn "*ashlhi3_1_lea"
[(set (attr "type")
(cond [(eq_attr "alternative" "1")
(const_string "lea")
- (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
+ (and (and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
@@ -9228,8 +9180,8 @@ (define_insn "*ashlhi3_1_lea"
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 ||
optimize_function_for_size_p (cfun)")
- (const_int 0)))))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p
(cfun)")))))
(const_string "0")
(const_string "*")))
(set_attr "mode" "HI,SI")])
@@ -9270,8 +9222,7 @@ (define_insn "*ashlqi3_1"
}
}
[(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
+ (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
@@ -9282,8 +9233,8 @@ (define_insn "*ashlqi3_1"
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 ||
optimize_function_for_size_p (cfun)")
- (const_int 0)))))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p
(cfun)")))))
(const_string "0")
(const_string "*")))
(set_attr "mode" "QI,SI")])
@@ -9330,8 +9281,7 @@ (define_insn "*ashlqi3_1_lea"
[(set (attr "type")
(cond [(eq_attr "alternative" "2")
(const_string "lea")
- (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
+ (and (and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
@@ -9342,8 +9292,8 @@ (define_insn "*ashlqi3_1_lea"
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 ||
optimize_function_for_size_p (cfun)")
- (const_int 0)))))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p
(cfun)")))))
(const_string "0")
(const_string "*")))
(set_attr "mode" "QI,SI,SI")])
@@ -9374,8 +9324,7 @@ (define_insn "*ashlqi3_1_slp"
}
}
[(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
+ (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 0 "register_operand" ""))
(match_operand 1 "const1_operand" ""))
(const_string "alu")
@@ -9386,8 +9335,8 @@ (define_insn "*ashlqi3_1_slp"
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift1")
(and (match_operand 1 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 ||
optimize_function_for_size_p (cfun)")
- (const_int 0)))))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p
(cfun)")))))
(const_string "0")
(const_string "*")))
(set_attr "mode" "QI")])
@@ -9471,8 +9420,7 @@ (define_insn "*ashl<mode>3_cmp"
}
}
[(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
+ (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
@@ -9483,8 +9431,8 @@ (define_insn "*ashl<mode>3_cmp"
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 ||
optimize_function_for_size_p (cfun)")
- (const_int 0)))))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p
(cfun)")))))
(const_string "0")
(const_string "*")))
(set_attr "mode" "<MODE>")])
@@ -9521,8 +9469,7 @@ (define_insn "*ashlsi3_cmp_zext"
}
}
[(set (attr "type")
- (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
+ (cond [(and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 2 "const1_operand" ""))
(const_string "alu")
]
@@ -9532,8 +9479,8 @@ (define_insn "*ashlsi3_cmp_zext"
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 ||
optimize_function_for_size_p (cfun)")
- (const_int 0)))))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p
(cfun)")))))
(const_string "0")
(const_string "*")))
(set_attr "mode" "SI")])
@@ -9567,8 +9514,7 @@ (define_insn "*ashl<mode>3_cconly"
}
}
[(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
+ (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
(match_operand 0 "register_operand" ""))
(match_operand 2 "const1_operand" ""))
(const_string "alu")
@@ -9579,8 +9525,8 @@ (define_insn "*ashl<mode>3_cconly"
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 ||
optimize_function_for_size_p (cfun)")
- (const_int 0)))))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p
(cfun)")))))
(const_string "0")
(const_string "*")))
(set_attr "mode" "<MODE>")])
@@ -9780,8 +9726,8 @@ (define_insn "*<shiftrt_insn><mode>3_1"
(set (attr "length_immediate")
(if_then_else
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p
(cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(const_string "*")))
(set_attr "mode" "<MODE>")])
@@ -9804,8 +9750,8 @@ (define_insn "*<shiftrt_insn>si3_1_zext"
(set (attr "length_immediate")
(if_then_else
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p
(cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(const_string "*")))
(set_attr "mode" "SI")])
@@ -9830,8 +9776,8 @@ (define_insn "*<shiftrt_insn>qi3_1_slp"
(set (attr "length_immediate")
(if_then_else
(and (match_operand 1 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p
(cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(const_string "*")))
(set_attr "mode" "QI")])
@@ -9865,8 +9811,8 @@ (define_insn "*<shiftrt_insn><mode>3_cmp
(set (attr "length_immediate")
(if_then_else
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p
(cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(const_string "*")))
(set_attr "mode" "<MODE>")])
@@ -9897,8 +9843,8 @@ (define_insn "*<shiftrt_insn>si3_cmp_zex
(set (attr "length_immediate")
(if_then_else
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p
(cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(const_string "*")))
(set_attr "mode" "SI")])
@@ -9927,8 +9873,8 @@ (define_insn "*<shiftrt_insn><mode>3_cco
(set (attr "length_immediate")
(if_then_else
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p
(cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(const_string "*")))
(set_attr "mode" "<MODE>")])
@@ -10077,8 +10023,8 @@ (define_insn "*<rotate_insn><mode>3_1"
(set (attr "length_immediate")
(if_then_else
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p
(cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(const_string "*")))
(set_attr "mode" "<MODE>")])
@@ -10101,8 +10047,8 @@ (define_insn "*<rotate_insn>si3_1_zext"
(set (attr "length_immediate")
(if_then_else
(and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p
(cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(const_string "*")))
(set_attr "mode" "SI")])
@@ -10127,8 +10073,8 @@ (define_insn "*<rotate_insn>qi3_1_slp"
(set (attr "length_immediate")
(if_then_else
(and (match_operand 1 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p
(cfun)")
- (const_int 0)))
+ (ior (match_test "TARGET_SHIFT1")
+ (match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(const_string "*")))
(set_attr "mode" "QI")])
@@ -15565,7 +15511,7 @@ (define_insn "*strmovqi_1"
(set_attr "memory" "both")
(set (attr "prefix_rex")
(if_then_else
- (ne (symbol_ref "<P:MODE>mode == DImode") (const_int 0))
+ (match_test "<P:MODE>mode == DImode")
(const_string "0")
(const_string "*")))
(set_attr "mode" "QI")])
@@ -15741,7 +15687,7 @@ (define_insn "*strsetqi_1"
(set_attr "memory" "store")
(set (attr "prefix_rex")
(if_then_else
- (ne (symbol_ref "<P:MODE>mode == DImode") (const_int 0))
+ (match_test "<P:MODE>mode == DImode")
(const_string "0")
(const_string "*")))
(set_attr "mode" "QI")])
@@ -15807,7 +15753,7 @@ (define_insn "*rep_stosqi"
(set_attr "memory" "store")
(set (attr "prefix_rex")
(if_then_else
- (ne (symbol_ref "<P:MODE>mode == DImode") (const_int 0))
+ (match_test "<P:MODE>mode == DImode")
(const_string "0")
(const_string "*")))
(set_attr "mode" "QI")])
@@ -15927,7 +15873,7 @@ (define_insn "*cmpstrnqi_nz_1"
(set_attr "mode" "QI")
(set (attr "prefix_rex")
(if_then_else
- (ne (symbol_ref "<P:MODE>mode == DImode") (const_int 0))
+ (match_test "<P:MODE>mode == DImode")
(const_string "0")
(const_string "*")))
(set_attr "prefix_rep" "1")])
@@ -15967,7 +15913,7 @@ (define_insn "*cmpstrnqi_1"
(set_attr "mode" "QI")
(set (attr "prefix_rex")
(if_then_else
- (ne (symbol_ref "<P:MODE>mode == DImode") (const_int 0))
+ (match_test "<P:MODE>mode == DImode")
(const_string "0")
(const_string "*")))
(set_attr "prefix_rep" "1")])
@@ -16008,7 +15954,7 @@ (define_insn "*strlenqi_1"
(set_attr "mode" "QI")
(set (attr "prefix_rex")
(if_then_else
- (ne (symbol_ref "<P:MODE>mode == DImode") (const_int 0))
+ (match_test "<P:MODE>mode == DImode")
(const_string "0")
(const_string "*")))
(set_attr "prefix_rep" "1")])
@@ -16435,7 +16381,7 @@ (define_insn "pro_epilogue_adjust_stack_
}
[(set (attr "type")
(cond [(and (eq_attr "alternative" "0")
- (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
+ (not (match_test "TARGET_OPT_AGU")))
(const_string "alu")
(match_operand:<MODE> 2 "const0_operand" "")
(const_string "imov")
Index: gcc/config/i386/mmx.md
===================================================================
--- gcc/config/i386/mmx.md 2011-08-13 11:06:03.000000000 +0100
+++ gcc/config/i386/mmx.md 2011-08-13 11:06:08.000000000 +0100
@@ -156,13 +156,13 @@ (define_insn "*mov<mode>_internal"
(if_then_else
(ior (eq_attr "alternative" "4,5")
(and (eq_attr "alternative" "7")
- (eq (symbol_ref "TARGET_AVX") (const_int 0))))
+ (not (match_test "TARGET_AVX"))))
(const_string "1")
(const_string "*")))
(set (attr "prefix_data16")
(if_then_else
(and (eq_attr "alternative" "8")
- (eq (symbol_ref "TARGET_AVX") (const_int 0)))
+ (not (match_test "TARGET_AVX")))
(const_string "1")
(const_string "*")))
(set (attr "prefix")
@@ -221,7 +221,7 @@ (define_insn "*movv2sf_internal_rex64"
(set (attr "length_vex")
(if_then_else
(and (eq_attr "alternative" "12,13")
- (ne (symbol_ref "TARGET_AVX") (const_int 0)))
+ (match_test "TARGET_AVX"))
(const_string "4")
(const_string "*")))
(set (attr "prefix")
@@ -1552,7 +1552,8 @@ (define_insn "*mmx_uavgv8qi3"
[(set_attr "type" "mmxshft")
(set (attr "prefix_extra")
(if_then_else
- (eq (symbol_ref "(TARGET_SSE || TARGET_3DNOW_A)") (const_int 0))
+ (not (ior (match_test "TARGET_SSE")
+ (match_test "TARGET_3DNOW_A")))
(const_string "1")
(const_string "*")))
(set_attr "mode" "DI")])
Index: gcc/config/i386/sse.md
===================================================================
--- gcc/config/i386/sse.md 2011-08-13 11:06:03.000000000 +0100
+++ gcc/config/i386/sse.md 2011-08-13 11:06:08.000000000 +0100
@@ -271,15 +271,13 @@ (define_insn "*mov<mode>_internal"
[(set_attr "type" "sselog1,ssemov,ssemov")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (cond [(ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (cond [(match_test "TARGET_AVX")
(const_string "<sseinsnmode>")
(ior (ior
- (ne (symbol_ref "optimize_function_for_size_p (cfun)")
- (const_int 0))
- (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
+ (match_test "optimize_function_for_size_p (cfun)")
+ (not (match_test "TARGET_SSE2")))
(and (eq_attr "alternative" "2")
- (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0))))
+ (match_test "TARGET_SSE_TYPELESS_STORES")))
(const_string "V4SF")
(eq (const_string "<MODE>mode") (const_string "V4SFmode"))
(const_string "V4SF")
@@ -422,7 +420,7 @@ (define_insn "*<sse2>_movdqu<avxsizesuff
(set_attr "movu" "1")
(set (attr "prefix_data16")
(if_then_else
- (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (match_test "TARGET_AVX")
(const_string "*")
(const_string "1")))
(set_attr "prefix" "maybe_vex")
@@ -438,12 +436,12 @@ (define_insn "<sse3>_lddqu<avxsizesuffix
(set_attr "movu" "1")
(set (attr "prefix_data16")
(if_then_else
- (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (match_test "TARGET_AVX")
(const_string "*")
(const_string "0")))
(set (attr "prefix_rep")
(if_then_else
- (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (match_test "TARGET_AVX")
(const_string "*")
(const_string "1")))
(set_attr "prefix" "maybe_vex")
@@ -478,7 +476,7 @@ (define_insn "<sse2>_movnt<mode>"
[(set_attr "type" "ssecvt")
(set (attr "prefix_data16")
(if_then_else
- (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (match_test "TARGET_AVX")
(const_string "*")
(const_string "1")))
(set_attr "prefix" "maybe_vex")
@@ -2038,7 +2036,7 @@ (define_insn "sse2_cvtps2dq"
[(set_attr "type" "ssecvt")
(set (attr "prefix_data16")
(if_then_else
- (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (match_test "TARGET_AVX")
(const_string "*")
(const_string "1")))
(set_attr "prefix" "maybe_vex")
@@ -2061,12 +2059,12 @@ (define_insn "sse2_cvttps2dq"
[(set_attr "type" "ssecvt")
(set (attr "prefix_rep")
(if_then_else
- (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (match_test "TARGET_AVX")
(const_string "*")
(const_string "1")))
(set (attr "prefix_data16")
(if_then_else
- (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (match_test "TARGET_AVX")
(const_string "*")
(const_string "0")))
(set_attr "prefix_data16" "0")
@@ -4147,7 +4145,7 @@ (define_insn "sse2_storehpd"
(set (attr "prefix_data16")
(if_then_else
(and (eq_attr "alternative" "0")
- (eq (symbol_ref "TARGET_AVX") (const_int 0)))
+ (not (match_test "TARGET_AVX")))
(const_string "1")
(const_string "*")))
(set_attr "prefix" "maybe_vex,orig,vex,*,*,*")
@@ -4377,7 +4375,7 @@ (define_insn "sse2_movsd"
(set (attr "prefix_data16")
(if_then_else
(and (eq_attr "alternative" "2,4")
- (eq (symbol_ref "TARGET_AVX") (const_int 0)))
+ (not (match_test "TARGET_AVX")))
(const_string "1")
(const_string "*")))
(set_attr "length_immediate" "*,*,*,*,*,1,*,*,*")
@@ -5735,9 +5733,9 @@ (define_insn "*andnot<mode>3"
(const_string "*")))
(set_attr "prefix" "orig,vex")
(set (attr "mode")
- (cond [(ne (symbol_ref "GET_MODE_SIZE (<MODE>mode) > 128") (const_int 0))
+ (cond [(match_test "GET_MODE_SIZE (<MODE>mode) > 128")
(const_string "V8SF")
- (ne (symbol_ref "TARGET_SSE2") (const_int 0))
+ (match_test "TARGET_SSE2")
(const_string "TI")
]
(const_string "V4SF")))])
@@ -5788,9 +5786,9 @@ (define_insn "*<code><mode>3"
(const_string "*")))
(set_attr "prefix" "orig,vex")
(set (attr "mode")
- (cond [(ne (symbol_ref "GET_MODE_SIZE (<MODE>mode) > 128") (const_int 0))
+ (cond [(match_test "GET_MODE_SIZE (<MODE>mode) > 128")
(const_string "V8SF")
- (ne (symbol_ref "TARGET_SSE2") (const_int 0))
+ (match_test "TARGET_SSE2")
(const_string "TI")
]
(const_string "V4SF")))])
@@ -6073,19 +6071,19 @@ (define_insn "<sse2p4_1>_pinsr<ssemodesu
(set_attr "type" "sselog")
(set (attr "prefix_rex")
(if_then_else
- (and (eq (symbol_ref "TARGET_AVX") (const_int 0))
+ (and (not (match_test "TARGET_AVX"))
(eq (const_string "<MODE>mode") (const_string "V2DImode")))
(const_string "1")
(const_string "*")))
(set (attr "prefix_data16")
(if_then_else
- (and (eq (symbol_ref "TARGET_AVX") (const_int 0))
+ (and (not (match_test "TARGET_AVX"))
(eq (const_string "<MODE>mode") (const_string "V8HImode")))
(const_string "1")
(const_string "*")))
(set (attr "prefix_extra")
(if_then_else
- (and (eq (symbol_ref "TARGET_AVX") (const_int 0))
+ (and (not (match_test "TARGET_AVX"))
(eq (const_string "<MODE>mode") (const_string "V8HImode")))
(const_string "*")
(const_string "1")))
@@ -6608,7 +6606,7 @@ (define_insn "*vec_concatv2di_rex64"
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "alternative" "0,3")
- (eq (symbol_ref "TARGET_AVX") (const_int 0)))
+ (not (match_test "TARGET_AVX")))
(const_string "1")
(const_string "*")))
(set_attr "prefix_extra" "1,1,*,*,*,*,*,*,*")
@@ -8060,7 +8058,7 @@ (define_insn "<sse4_1>_round<ssemodesuff
[(set_attr "type" "ssecvt")
(set (attr "prefix_data16")
(if_then_else
- (ne (symbol_ref "TARGET_AVX") (const_int 0))
+ (match_test "TARGET_AVX")
(const_string "*")
(const_string "1")))
(set_attr "prefix_extra" "1")
