On Wed, Jul 20, 2011 at 6:41 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
> On Wed, Jul 20, 2011 at 3:18 PM, H.J. Lu <hjl.to...@gmail.com> wrote:
>> On Wed, Jul 20, 2011 at 1:19 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
>>> On Wed, Jul 20, 2011 at 9:53 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
>>>
>>>>>>>> since Pmode is used in non-PIC tablejump, we have to put 64bit value
>>>>>>>> for
>>>>>>>> labels with 0 upper 32bits in tablejump for x32.
>>>>>>>
>>>>>>> The mode is completely controled by CASE_VECTOR_MODE.
>>>>>>>
>>>>>>
>>>>>> Here is the updated patch. OK for trunk?
>>>>>>
>>>>>
>>>>> A small change. It always use 64bit register for indirect branch.
>>>>
>>>> - ix86_print_operand (file, x, 0);
>>>> + /* Always use 64bit register for indirect branch. */
>>>> + ix86_print_operand (file, x,
>>>> + REG_P (x) && TARGET_64BIT ? 'q' : 0);
>>>> return;
>>>>
>>>> /* Always use 64bit register for indirect branch. */
>>>> if (REG_P (x) && TARGET_64BIT)
>>>> print_reg (x, 'q', file);
>>>> else
>>>> ix86_print_operand (file, x, 0);
>>>>
>>>> (define_insn "*indirect_jump"
>>>> - [(set (pc) (match_operand:P 0 "nonimmediate_operand" "rm"))]
>>>> + [(set (pc) (match_operand:P 0 "x32_indirect_branch_operand" "rm"))]
>>>>
>>>> Just name it "indirect_branch_operand".
>>>>
>>>> (define_insn_and_split "*call_vzeroupper"
>>>> - [(call (mem:QI (match_operand:P 0 "call_insn_operand" "<c>zm"))
>>>> + [(call (mem:QI (match_operand:P 0 "x32_call_insn_operand" "<c>zm"))
>>>>
>>>> Don't introduce new predicate, change call_insn_operand instead to
>>>> conditionally disable memory_operand on x32. You will need to change
>>>> "<c>zm" register constraint to "<c>z" on x32, otherwise you will get
>>>> ICEs.
>>>
>>> Use new constraint here, something like (untested):
>>>
>>> Index: constraints.md
>>> ===================================================================
>>> --- constraints.md (revision 176494)
>>> +++ constraints.md (working copy)
>>> @@ -127,6 +127,11 @@
>>> "@internal Constant call address operand."
>>> (match_operand 0 "constant_call_address_operand"))
>>>
>>> +(define_constraint "w"
>>> + "@internal Call memory operand."
>>> + (and (match_test "!TARGET_X32")
>>> + (match_operand 0 "memory_operand"))
>>> +
>>> ;; Integer constant constraints.
>>> (define_constraint "I"
>>> "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
>>>
>>> Uros.
>>>
>>
>> Here is the updated patch. OK for trunk?
>>
>> Thanks.
>>
>> --
>> H.J.
>> -----
>> 2011-07-20 H.J. Lu <hongjiu...@intel.com>
>> Uros Bizjak <ubiz...@gmail.com>
>>
>> * config/i386/constraints.md (w): New.
>>
>> * config/i386/i386.c (ix86_print_operand): Always use 64bit
>> register for indirect branch.
>> (ix86_output_addr_vec_elt): Check TARGET_LP64 instead of
>> TARGET_64BIT for ASM_QUAD.
>>
>> * config/i386/i386.h (CASE_VECTOR_MODE): Check TARGET_LP64
>> instead of TARGET_64BIT.
>>
>> * config/i386/i386.md (*indirect_jump): Replace
>> nonimmediate_operand with indirect_branch_operand.
>> (*tablejump_1): Likewise.
>> (*call_vzeroupper): Replace constraint "m" with "w".
>> (*call): Likewise.
>> (*call_rex64_ms_sysv_vzeroupper): Likewise.
>> (*call_rex64_ms_sysv): Likewise.
>> (*call_value_vzeroupper): Likewise.
>> (*call_value): Likewise.
>> (*call_value_rex64_ms_sysv_vzeroupper): Likewise.
>> (*call_value_rex64_ms_sysv): Likewise.
>> (*tablejump_1_x32): New.
>> (set_got_offset_rex64): Check TARGET_LP64 instead of
>> TARGET_64BIT.
>>
>> * config/i386/predicates.md (indirect_branch_operand): New.
>> (call_insn_operand): Support x32.
>>
>
> +
> +(define_insn "*tablejump_1_x32"
> + [(set (pc) (match_operand:SI 0 "register_operand" "r"))
> + (use (label_ref (match_operand 1 "" "")))]
> + "TARGET_X32"
> + "jmp\t%A0"
> + [(set_attr "type" "ibr")
> + (set_attr "length_immediate" "0")])
>
> This pattern should include zero_extend from operand 0. Please fix the
> tablejump expander to generate correct pattern.
>
> Also, indirect jump needs to generate zero_extend from SImode register for
> x32.
>
I am testing this patch on top of the last one. We don't need to zero-extend
indirect jump since it takes operand 0 in Pmode, which is DImode.
--
H.J.
---
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 708cfa5..43a753d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10982,7 +10982,7 @@
(set_attr "modrm" "0")])
(define_expand "indirect_jump"
- [(set (pc) (match_operand 0 "nonimmediate_operand" ""))])
+ [(set (pc) (match_operand 0 "indirect_branch_operand" ""))])
(define_insn "*indirect_jump"
[(set (pc) (match_operand:P 0 "indirect_branch_operand" "rw"))]
@@ -10992,7 +10992,7 @@
(set_attr "length_immediate" "0")])
(define_expand "tablejump"
- [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" ""))
+ [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand" ""))
(use (label_ref (match_operand 1 "" "")))])]
""
{
@@ -11027,6 +11027,8 @@
operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
OPTAB_DIRECT);
}
+ else if (TARGET_X32)
+ operands[0] = gen_rtx_ZERO_EXTEND (Pmode, operands[0]);
})
(define_insn "*tablejump_1"
@@ -11038,7 +11040,8 @@
(set_attr "length_immediate" "0")])
(define_insn "*tablejump_1_x32"
- [(set (pc) (match_operand:SI 0 "register_operand" "r"))
+ [(set (pc) (zero_extend:DI
+ (match_operand:SI 0 "register_operand" "r")))
(use (label_ref (match_operand 1 "" "")))]
"TARGET_X32"
"jmp\t%A0"
