On 16 January 2015 at 14:56, Tejas Belagod <tejas.bela...@arm.com> wrote:
>> +#ifndef NO_FLOAT_VARIANT
>> + VLOAD(vector, buffer, , float, f, 32, 2);
>> + VLOAD(vector, buffer, q, float, f, 32, 4);
>> +#endif
>>
> ....
>>
>> +#ifndef NO_FLOAT_VARIANT
>> + VDUP(vector2, , float, f, 32, 2, -15.5f);
>> + VDUP(vector2, q, float, f, 32, 4, -14.5f);
>> +#endif
>> +
>> +#ifndef NO_FLOAT_VARIANT
>> +#define FLOAT_VARIANT(MACRO, VAR) \
>> + MACRO(VAR, , float, f, 32, 2); \
>> + MACRO(VAR, q, float, f, 32, 4)
>> +#else
>> +#define FLOAT_VARIANT(MACRO, VAR)
>> +#endif
>
>
> Double negative! :-) Probably easier on the reader to avoid it, but your
> call.
Oh yes... I am importing my existing code, so I try to minimize changes.
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
>> new file mode 100644
>> index 0000000..2591b16
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
>> @@ -0,0 +1,64 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +#define INSN_NAME vmax
>> +#define TEST_MSG "VMAX/VMAXQ"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
>> + 0xf4, 0xf5, 0xf6, 0xf7 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
>> + 0xf4, 0xf5, 0xf6, 0xf7 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff3
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1780000, 0xc1700000 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xf4, 0xf4, 0xf4, 0xf4,
>> + 0xf4, 0xf5, 0xf6, 0xf7,
>> + 0xf8, 0xf9, 0xfa, 0xfb,
>> + 0xfc, 0xfd, 0xfe, 0xff };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3,
>> + 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
>> + 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf9, 0xf9, 0xf9, 0xf9,
>> + 0xf9, 0xf9, 0xf9, 0xf9,
>> + 0xf9, 0xf9, 0xfa, 0xfb,
>> + 0xfc, 0xfd, 0xfe, 0xff };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3,
>> + 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1,
>> + 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1680000, 0xc1680000,
>> + 0xc1600000, 0xc1500000 };
>> +
>> +/* Expected results with special FP values. */
>> +VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
>> + 0x7fc00000, 0x7fc00000 };
>> +VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
>> + 0x7fc00000, 0x7fc00000 };
>> +VECT_VAR_DECL(expected_inf,hfloat,32,4) [] = { 0x7f800000, 0x7f800000,
>> + 0x7f800000, 0x7f800000 };
>> +VECT_VAR_DECL(expected_minf,hfloat,32,4) [] = { 0x3f800000, 0x3f800000,
>> + 0x3f800000, 0x3f800000 };
>> +VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>> +VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>> +
>> +#include "binary_op_no64.inc"
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
>> new file mode 100644
>> index 0000000..2b5e87c
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
>> @@ -0,0 +1,66 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +#define INSN_NAME vmin
>> +#define TEST_MSG "VMIN/VMINQ"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf3, 0xf3, 0xf3, 0xf3 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf3, 0xf3, 0xf3, 0xf3 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff1, 0xfff1
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1780000 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf4, 0xf4, 0xf4, 0xf4,
>> + 0xf4, 0xf4, 0xf4, 0xf4,
>> + 0xf4, 0xf4, 0xf4, 0xf4 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
>> + 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
>> + 0xfffffff1, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf4, 0xf5, 0xf6, 0xf7,
>> + 0xf8, 0xf9, 0xf9, 0xf9,
>> + 0xf9, 0xf9, 0xf9, 0xf9 };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2,
>> + 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
>> + 0xfffffff1, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
>> + 0xc1680000, 0xc1680000 };
>> +/* Expected results with special FP values. */
>> +VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
>> + 0x7fc00000, 0x7fc00000 };
>> +VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
>> + 0x7fc00000, 0x7fc00000 };
>> +VECT_VAR_DECL(expected_inf,hfloat,32,4) [] = { 0x3f800000, 0x3f800000,
>> + 0x3f800000, 0x3f800000 };
>> +VECT_VAR_DECL(expected_minf,hfloat,32,4) [] = { 0xff800000, 0xff800000,
>> + 0xff800000, 0xff800000 };
>> +VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] = { 0x80000000, 0x80000000,
>> + 0x80000000, 0x80000000 };
>> +VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] = { 0x80000000, 0x80000000,
>> + 0x80000000, 0x80000000 };
>> +
>> +#include "binary_op_no64.inc"
>
>
> vmax and vmin do have v<maxmin>_f64 and v<maxmin>q_f64 variants.
My existing tests only cover armv7 so far.
I do plan to expand them once they are all in GCC.
> Otherwise, they look good to me(but I can't approve it).
>
> Tejas.
>
