Hello!
2011-06-05 Uros Bizjak <ubiz...@gmail.com>
* config/i386/i386.md (*movdf_internal_rex64) <case 8,9,10>:
Remove MODE_TI handling. Remove SSE1 handling in attribute "mode"
calculation.
(*movdf_internal_rex64) <case 6,7,8>: Remove MODE_TI handling.
Simplify MODE_V1DF and MODE_V2SF handling.
(*movsf_internal): Remove x constraint from operand 1 alternative 7.
Simplify MODE_SF handling.
Patch was bootstrapped and regression tested on x86_64-pc-linux-gnuj
{,-m32} AVX target. Committed to mainline SVN.
Uros.
Index: i386.md
===================================================================
--- i386.md (revision 174655)
+++ i386.md (working copy)
@@ -2956,9 +2956,6 @@
case 10:
switch (get_attr_mode (insn))
{
- case MODE_TI:
- if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vmovdqa\t{%1, %0|%0, %1}";
case MODE_V2DF:
if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
return "%vmovapd\t{%1, %0|%0, %1}";
@@ -2970,8 +2967,7 @@
case MODE_DF:
if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
- else
- return "%vmovsd\t{%1, %0|%0, %1}";
+ return "%vmovsd\t{%1, %0|%0, %1}";
case MODE_V1DF:
return "%vmovlpd\t{%1, %d0|%d0, %1}";
case MODE_V2SF:
@@ -3014,13 +3010,6 @@
(eq_attr "alternative" "3,4,5,6,11,12")
(const_string "DI")
- /* For SSE1, we have many fewer alternatives. */
- (eq (symbol_ref "TARGET_SSE2") (const_int 0))
- (cond [(eq_attr "alternative" "7,8")
- (const_string "V4SF")
- ]
- (const_string "V2SF"))
-
/* xorps is one byte shorter. */
(eq_attr "alternative" "7")
(cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
@@ -3099,9 +3088,6 @@
case 8:
switch (get_attr_mode (insn))
{
- case MODE_TI:
- if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vmovdqa\t{%1, %0|%0, %1}";
case MODE_V2DF:
if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
return "%vmovapd\t{%1, %0|%0, %1}";
@@ -3113,18 +3099,11 @@
case MODE_DF:
if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
- else
- return "%vmovsd\t{%1, %0|%0, %1}";
+ return "%vmovsd\t{%1, %0|%0, %1}";
case MODE_V1DF:
- if (TARGET_AVX && REG_P (operands[0]))
- return "vmovlpd\t{%1, %0, %0|%0, %0, %1}";
- else
- return "%vmovlpd\t{%1, %0|%0, %1}";
+ return "%vmovlpd\t{%1, %d0|%d0, %1}";
case MODE_V2SF:
- if (TARGET_AVX && REG_P (operands[0]))
- return "vmovlps\t{%1, %0, %0|%0, %0, %1}";
- else
- return "%vmovlps\t{%1, %0|%0, %1}";
+ return "%vmovlps\t{%1, %d0|%d0, %1}";
default:
gcc_unreachable ();
}
@@ -3150,9 +3129,9 @@
/* For SSE1, we have many fewer alternatives. */
(eq (symbol_ref "TARGET_SSE2") (const_int 0))
- (cond [(eq_attr "alternative" "5,6")
- (const_string "V4SF")
- ]
+ (if_then_else
+ (eq_attr "alternative" "5,6")
+ (const_string "V4SF")
(const_string "V2SF"))
/* xorps is one byte shorter. */
@@ -3195,9 +3174,9 @@
(define_insn "*movsf_internal"
[(set (match_operand:SF 0 "nonimmediate_operand"
- "=f,m,f,?r ,?m,x,x,x ,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
+ "=f,m,f,?r ,?m,x,x,x,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
(match_operand:SF 1 "general_operand"
- "fm,f,G,rmF,Fr,C,x,xm,x,m ,*y,*y ,r ,Yi,r ,*Ym"))]
+ "fm,f,G,rmF,Fr,C,x,m,x,m ,*y,*y ,r ,Yi,r ,*Ym"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (!can_create_pseudo_p ()
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
@@ -3228,23 +3207,24 @@
case 6:
if (get_attr_mode (insn) == MODE_V4SF)
return "%vmovaps\t{%1, %0|%0, %1}";
- else
- return "%vmovss\t{%1, %d0|%d0, %1}";
+
case 7:
- if (TARGET_AVX && REG_P (operands[1]))
- return "vmovss\t{%1, %0, %0|%0, %0, %1}";
- else
- return "%vmovss\t{%1, %0|%0, %1}";
case 8:
+ if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
+ return "vmovss\t{%1, %0, %0|%0, %0, %1}";
return "%vmovss\t{%1, %0|%0, %1}";
- case 9: case 10: case 14: case 15:
+ case 9:
+ case 10:
+ case 14:
+ case 15:
return "movd\t{%1, %0|%0, %1}";
case 11:
return "movq\t{%1, %0|%0, %1}";
- case 12: case 13:
+ case 12:
+ case 13:
return "%vmovd\t{%1, %0|%0, %1}";
default:
