[Bug target/127269] [17 Regression] [RISC-V] ICE in riscv_v_widen_constraint_ok during IRA pass with -march=rv64gcv

[groche97 at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127269

--- Comment #5 from groche97 at gmail dot com ---
Maybe this must be another bug, but looks very similar, other ICE with a vwmacc
instead of a vwmul, after apply the patch that fix the previous testcase:

#include <riscv_vector.h>

vint32m2_t f(vint16m4_t p1, vint32m2_t p2) {
        vint16m1_t a = __riscv_vget_v_i16m4_i16m1(p1, 0);
        vint32m2_t b = __riscv_vwmacc_vx_i32m2(p2, 1, a, 0);
        return b;
}