[Bug target/127269] [17 Regression] [RISC-V] ICE in riscv_v_widen_constraint_ok during IRA pass with -march=rv64gcv

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127269

Drea Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |17.0
            Summary|[RISC-V] ICE in             |[17 Regression] [RISC-V]
                   |riscv_v_widen_constraint_ok |ICE in
                   |during IRA pass with        |riscv_v_widen_constraint_ok
                   |-march=rv64gcv              |during IRA pass with
                   |                            |-march=rv64gcv
             Target|                            |riscv
           Keywords|                            |ice-on-valid-code