https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127269
--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Pan Li <[email protected]>: https://gcc.gnu.org/g:1f3017b56321ee05a4ffd5615285045ba8816753 commit r17-4183-g1f3017b56321ee05a4ffd5615285045ba8816753 Author: Pan Li <[email protected]> Date: Thu Sep 10 10:01:56 2026 +0800 RISC-V: Fix ICE for widening insn when dest and src LMUL are equal [PR target/127269] The function riscv_v_widen_constraint_ok asserts the nregs must be 1 when the dest and the src have the same number of registers. That is not always true, for example the vwmul.vv with the src comes from the vget of one wider vector register group. Then we may have both the dest and the src take 2 registers and result in the ICE as below. during RTL pass: reload pr127269-1.c:12:1: internal compiler error: in riscv_v_widen_constraint_ok, at config/riscv/riscv-v.cc:6558 Thus, take the register overlap as not allowed instead of the assertion when the dest and the src have the same nregs but the nregs is greater than 1. PR target/127269 gcc/ChangeLog: * config/riscv/riscv-v.cc (riscv_v_widen_constraint_ok): Return false instead of assertion when the nregs of dest and src are the same but greater than 1. Signed-off-by: Pan Li <[email protected]>
