[Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen

[kito at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

Kito Cheng <kito at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |kito at gcc dot gnu.org

--- Comment #8 from Kito Cheng <kito at gcc dot gnu.org> ---
This topic has raised at last RISC-V GCC sync meeting, and one action item for
me is chat with JuzheZhong about -mrvv-vector-bits=zvl / __riscv_v_fixed_vlen /
riscv_rvv_vector_bits stuffs