[Bug target/108185] New: [RISC-V]RVV assemble not set vsetvli correct.

[jiawei at iscas dot ac.cn via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185

            Bug ID: 108185
           Summary: [RISC-V]RVV assemble not set vsetvli correct.
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jiawei at iscas dot ac.cn
  Target Milestone: ---

Currently, when use gcc13 to compile follow code with rvv
extension(-march=rv64gcv -O3),


  void foo5_3 (int32_t * restrict in, int32_t * restrict out, size_t n, int
cond)
  {
    vint8m1_t v = *(vint8m1_t*)in;
    *(vint8m1_t*)out = v;
    vbool8_t v3 = *(vbool8_t*)in;
    *(vbool8_t*)(out + 200) = v3;
  }

it will generate asm as:

  vl1re8.v        v25,0(a0)
  sub     a5,a3,a5
  vs1r.v  v25,0(a1)
  vs1r.v  v25,0(a5)

seems not use vsetvli correctly, any suggestions?