https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106069
--- Comment #16 from luoxhu at gcc dot gnu.org ---
The attached files are all built with -mcpu=power8 and the case also fails on
P8LE.
Also I verified the code produces expected output on P8BE. ('Aborted' is caused
by BE returns 0x41 instead of 0x98 for LE.)
P8LE &P9LE:
luoxhu@gcc135 build $ ./q.bad
B0: 0, 0,0,0
Aborted
P8BE:
luoxhu@gcc203:~/workspace/build$ ./q.bad
B0: 41fcef98, 91648e8b,7dca18c6,61707865
Aborted
P8BE seems generates better code with the patch:
luoxhu@gcc203:~/workspace/build$ diff q.good.S q.bad.S -U5
--- q.good.S 2022-07-26 09:19:32.487216946 +0300
+++ q.bad.S 2022-07-26 09:15:58.006770996 +0300
@@ -1,6 +1,7 @@
.file "q.C"
+ .machine power8
.section ".text"
.section .rodata.str1.8,"aMS",@progbits,1
.align 3
.LC0:
.string "B0: %x, %x,%x,%x\n"
@@ -24,19 +25,17 @@
.cfi_def_cfa_offset 128
.cfi_offset 65, 16
.cfi_offset 30, -16
.cfi_offset 31, -8
mr %r30,%r3
- vmrghw %v2,%v2,%v4
- vmrghw %v5,%v3,%v5
- vmrghw %v5,%v2,%v5
- vspltw %v0,%v5,3
+ vspltw %v0,%v5,0
mfvsrwz %r7,%vs32
- vspltw %v0,%v5,2
+ vspltw %v0,%v4,0
mfvsrwz %r6,%vs32
- mfvsrwz %r5,%vs37
- vspltw %v0,%v5,0
+ vspltw %v0,%v3,0
+ mfvsrwz %r5,%vs32
+ vspltw %v0,%v2,0
mfvsrwz %r31,%vs32
rldicl %r7,%r7,0,32
rldicl %r6,%r6,0,32
rldicl %r5,%r5,0,32
rldicl %r4,%r31,0,32
@@ -169,6 +168,6 @@
.set .LANCHOR1,. + 0
.type res, @object
.size res, 1
res:
.zero 1
- .ident "GCC: (Debian 9.5.0-1) 9.5.0"
+ .ident "GCC: (GNU) 13.0.0 20220726 (experimental)"
