On Wed, Apr 1, 2020 at 6:58 PM Christo Crause <christo.cra...@gmail.com>
wrote:
> Good idea, the alternative instructions are part of the core ISA so it
> should always be supported.
>
So the updated cgcpu patch attached...
diff --git a/compiler/xtensa/cgcpu.pas b/compiler/xtensa/cgcpu.pas
index a1fdbede87..25b6cb40b9 100644
--- a/compiler/xtensa/cgcpu.pas
+++ b/compiler/xtensa/cgcpu.pas
@@ -167,14 +167,26 @@ implementation
list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,8));
OS_S8:
begin
- list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,7));
+ if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
+ list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,7))
+ else
+ begin
+ list.concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,24));
+ list.concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,24));
+ end;
if tosize=OS_16 then
list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg2,0,16));
end;
OS_16:
list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,16));
OS_S16:
- list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,15));
+ if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
+ list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,15))
+ else
+ begin
+ list.concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,16));
+ list.concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,16));
+ end;
else
conv_done:=false;
end;
@@ -258,7 +270,13 @@ implementation
list.concat(taicpu.op_reg_ref(op,reg,href));
if (fromsize=OS_S8) and not(tosize in [OS_S8,OS_8]) then
- list.concat(taicpu.op_reg_reg_const(A_SEXT,reg,reg,7));
+ if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
+ list.concat(taicpu.op_reg_reg_const(A_SEXT,reg,reg,7))
+ else
+ begin
+ list.concat(taicpu.op_reg_reg_const(A_SLLI,reg,reg,24));
+ list.concat(taicpu.op_reg_reg_const(A_SRAI,reg,reg,24));
+ end;
if (fromsize<>tosize) and (not (tosize in [OS_SINT,OS_INT])) then
a_load_reg_reg(list,fromsize,tosize,reg,reg);
end;
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