On Tue, Mar 31, 2020 at 7:39 AM Sven Barth via fpc-devel < fpc-devel@lists.freepascal.org> wrote:
> Am 30.03.2020 um 22:07 schrieb Christo Crause via fpc-devel: > > > On Sun, Mar 29, 2020 at 11:00 PM Florian Klämpfl <flor...@freepascal.org> > wrote: > >> Am 29.03.20 um 22:46 schrieb Christo Crause via fpc-devel: >> > It seems that a different instruction sequence should be used for sign >> > extension for the lx106 subarch. >> >> Ok, I see. Let me first integrate everything done so far in trunk, then >> we can continue with the details :) >> > > I've noticed GCC uses the SLLI + SRAI instructions to perform sign > extension on ESP8266. > > Since different CPUs can support different subsets of the Xtensa > instructions do you think a finalizecode type function can be used as a > post code generation step to map unsupported instructions to alternative > sequences? > > > These are simply different CPU types (-CpXXX or selected by the controller > type) which the code generator will handle accordingly. Just like it's done > with ARM, AVR and all other platforms. > Make sense. The make files are not current set up like that for xtensa. I'll make a patch to make xtensa-embedded work like avr etc with regards to subarch. This will then make it easier to check for cpu_capabilities in the compiler.
_______________________________________________ fpc-devel maillist - fpc-devel@lists.freepascal.org https://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel
