On Wednesday 22 May 2013 15:49:22 Jon Elson did opine:

> Gene Heskett wrote:
> > Perhaps the next generation of devices
> > that may come out of the next shrink might find a better geometry to
> > alleviate this?
> 
> There probably won't be any "shrinks" with the current Silicon
> technology, I think the MOSFET is pretty mature.  They are trying, but
> it looks like they
> have pretty much hit their own "Moore's wall",

Higher voltages seems to enforce that.

> and further improvements
> are in very small steps.  Mostly they are working to improve reliability
> under high-voltage switching avalanche conditions.
> 
Yet another failure mechanism that can let all the smoke out in 10 u-secs.

> Eventually, some other technology may take over, SiC, SiN or something.
> 
> But, a low enough drive impedance, and it doesn't have to be massively
> low, will prevent unwanted turn-on even when the D-S voltage has
> a rapid rise.  The calculation is easy, just I = dV/dT * Cm, where Cm
> is the Miller capacitance.  As long as the driver impedance + gate
> resistor keeps the gate below the threshold, the transistor stays off.
> 
> Jon
 
I think you just said it better than I could.  I've been too far away for 
too long I guess.

Thanks Jon.

Cheers, Gene
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