Gene Heskett wrote: > > So the problem isn't amenable to just delaying the on drive. I take it > that a hard and stiff off bias is simply swamped by the DvDt induced > capacitance charge from drain to gate. > > No, not swamped. You can calculate the amount of gate current that has to be drained to keep the transistor off when it is supposed to be off, based on the dV/dT of the turning-on transistor. It isn't any greater than the gate current required to turn the transistor on quickly, so the same driver circuitry handles both conditions. > I also have to assume that tech writers 20 years ago didn't always > understand the phenomenon they were writing about, because then the holy > grail was just getting rid of any both on at the same time, eg they weren't > sure of the causal mechanism. So my knowledge expands a bit. > > Oh, I think the app engineers understood this quite well 20 years ago. Whether particular magazine articles expressed it clearly may be another matter, but I think it was certainly pretty clear in the literature. IR published a HUGE amount of tech data themselves that went through all these issues in sample designs. > Now I wander into theory Peter, because it seems to me that with low enough > impedance in the drive, if it getting turned back on for a microsec or so, > that should be something that a better and lower resistance from the gate > terminal to the gate area of the die ought to be able to absorb that. > Perhaps the next generation of devices that may come out of the next shrink > might find a better geometry to alleviate this? > There probably won't be any "shrinks" with the current Silicon technology, I think the MOSFET is pretty mature. They are trying, but it looks like they have pretty much hit their own "Moore's wall", and further improvements are in very small steps. Mostly they are working to improve reliability under high-voltage switching avalanche conditions.
Eventually, some other technology may take over, SiC, SiN or something. But, a low enough drive impedance, and it doesn't have to be massively low, will prevent unwanted turn-on even when the D-S voltage has a rapid rise. The calculation is easy, just I = dV/dT * Cm, where Cm is the Miller capacitance. As long as the driver impedance + gate resistor keeps the gate below the threshold, the transistor stays off. Jon ------------------------------------------------------------------------------ Try New Relic Now & We'll Send You this Cool Shirt New Relic is the only SaaS-based application performance monitoring service that delivers powerful full stack analytics. Optimize and monitor your browser, app, & servers with just a few lines of code. Try New Relic and get this awesome Nerd Life shirt! http://p.sf.net/sfu/newrelic_d2d_may _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
