As result of recent re-design of the MSI/MSI-X interrupts enabling pattern this driver has to be updated to use the new technique to obtain a optimal number of MSI/MSI-X interrupts required.
Signed-off-by: Alexander Gordeev <[email protected]> --- drivers/net/ethernet/broadcom/tg3.c | 24 +++++++++++++----------- 1 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 12d961c..2e842ef3 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -11241,6 +11241,10 @@ static bool tg3_enable_msix(struct tg3 *tp) int i, rc; struct msix_entry msix_ent[TG3_IRQ_MAX_VECS]; + rc = pci_msix_table_size(tp->pdev); + if (rc < 0) + return false; + tp->txq_cnt = tp->txq_req; tp->rxq_cnt = tp->rxq_req; if (!tp->rxq_cnt) @@ -11256,6 +11260,14 @@ static bool tg3_enable_msix(struct tg3 *tp) tp->txq_cnt = 1; tp->irq_cnt = tg3_irq_count(tp); + if (tp->irq_cnt > rc) { + netdev_notice(tp->dev, "Requested %d MSI-Xs, available %d\n", + tp->irq_cnt, rc); + tp->irq_cnt = rc; + tp->rxq_cnt = max(rc - 1, 1); + if (tp->txq_cnt) + tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); + } for (i = 0; i < tp->irq_max; i++) { msix_ent[i].entry = i; @@ -11263,18 +11275,8 @@ static bool tg3_enable_msix(struct tg3 *tp) } rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); - if (rc < 0) { + if (rc) return false; - } else if (rc != 0) { - if (pci_enable_msix(tp->pdev, msix_ent, rc)) - return false; - netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", - tp->irq_cnt, rc); - tp->irq_cnt = rc; - tp->rxq_cnt = max(rc - 1, 1); - if (tp->txq_cnt) - tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); - } for (i = 0; i < tp->irq_max; i++) tp->napi[i].irq_vec = msix_ent[i].vector; -- 1.7.7.6 ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134791&iu=/4140/ostg.clktrk _______________________________________________ E1000-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
