ср, 30 вер. 2026 р. о 11:35 Thierry Reding <[email protected]> пише: > > On Wed, Sep 30, 2026 at 10:05:30AM +0300, Svyatoslav Ryhel wrote: > > Expand existing DC register definitions with additional fields in > > preparation for adding the 8-bit CPU interface. > > > > Signed-off-by: Svyatoslav Ryhel <[email protected]> > > --- > > drivers/gpu/drm/tegra/dc.c | 3 ++- > > drivers/gpu/drm/tegra/dc.h | 54 ++++++++++++++++++++++++++++++++++---- > > 2 files changed, 51 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > > index b0bfa946e6979..5c67928bcabfa 100644 > > --- a/drivers/gpu/drm/tegra/dc.c > > +++ b/drivers/gpu/drm/tegra/dc.c > > @@ -2384,7 +2384,8 @@ static void tegra_crtc_atomic_enable(struct drm_crtc > > *crtc, > > > > if (dc->rgb) { > > /* XXX: parameterize? */ > > - value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE; > > + value = SC0_H_QUALIFIER(SC_H_QUALIFIER_NONE) | > > + SC1_H_QUALIFIER(SC_H_QUALIFIER_NONE); > > tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); > > } > > > > diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h > > index 0cb0515968b35..5679e1ca0c2a5 100644 > > --- a/drivers/gpu/drm/tegra/dc.h > > +++ b/drivers/gpu/drm/tegra/dc.h > > @@ -274,8 +274,11 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); > > #define DC_COM_CRC_CHECKSUM 0x301 > > #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) > > #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) > > +#define LSC0_OUTPUT_POLARITY_LOW BIT(24) > > #define LVS_OUTPUT_POLARITY_LOW (1 << 28) > > #define LHS_OUTPUT_POLARITY_LOW (1 << 30) > > +#define LSPI_OUTPUT_POLARITY_LOW BIT(8) > > +#define LDC_OUTPUT_SELECT_V_PULSE1 BIT(14) > > #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x)) > > #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x)) > > #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x)) > > @@ -303,9 +306,15 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); > > #define UNDERFLOW_REPORT_ENABLE (1 << 0) > > > > #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 > > -#define H_PULSE0_ENABLE (1 << 8) > > -#define H_PULSE1_ENABLE (1 << 10) > > -#define H_PULSE2_ENABLE (1 << 12) > > +#define H_PULSE0_ENABLE BIT(8) > > +#define H_PULSE1_ENABLE BIT(10) > > +#define H_PULSE2_ENABLE BIT(12) > > +#define V_PULSE0_ENABLE BIT(16) > > +#define V_PULSE1_ENABLE BIT(18) > > +#define V_PULSE2_ENABLE BIT(19) > > +#define V_PULSE3_ENABLE BIT(20) > > +#define M0_ENABLE BIT(24) > > +#define M1_ENABLE BIT(26) > > > > #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 > > > > @@ -451,11 +460,30 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); > > #define BASE_COLOR_SIZE_888 ( 8 << 0) > > #define BASE_COLOR_SIZE_101010 ( 10 << 0) > > #define BASE_COLOR_SIZE_121212 ( 12 << 0) > > +#define DISP_COLOR_SWAP_BGR BIT(16) > > #define CMU_ENABLE_ENABLE (1 << 20) > > > > #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 > > -#define SC1_H_QUALIFIER_NONE (1 << 16) > > -#define SC0_H_QUALIFIER_NONE (1 << 0) > > +#define SC0_H_QUALIFIER(x) (((x) & 0x7) << 0) > > +#define SC1_H_QUALIFIER(x) (((x) & 0x7) << 16) > > +enum { > > + SC_H_QUALIFIER_DISABLE, > > + SC_H_QUALIFIER_NONE, > > + SC_H_QUALIFIER_HACTIVE, > > + SC_H_QUALIFIER_EXT_HACTIVE, > > + SC_H_QUALIFIER_HPULSE, > > + SC_H_QUALIFIER_EXT_HPULSE, > > +}; > > Let's stick with regular defines for this, there's really no advantage > in using enums for this and the other enums introduced by this patch. >
Alright, noted. Thanks. > Thierry
