Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] drm/tegra: suspected typo in V_PULSE2/3_ENABLE bit definitions --
commit e8ce1bb59e056f4559d5bb8b73b971c10b8c4d5a Author: Svyatoslav Ryhel <[email protected]> drm/tegra: dc: Expand available registers layouts This commit expands existing display controller register definitions with additional fields in preparation for adding an 8-bit CPU interface. > diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h > --- a/drivers/gpu/drm/tegra/dc.h > +++ b/drivers/gpu/drm/tegra/dc.h [ ... ] > @@ -303,9 +306,15 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); > #define UNDERFLOW_REPORT_ENABLE (1 << 0) > > #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 > -#define H_PULSE0_ENABLE (1 << 8) > -#define H_PULSE1_ENABLE (1 << 10) > -#define H_PULSE2_ENABLE (1 << 12) > +#define H_PULSE0_ENABLE BIT(8) > +#define H_PULSE1_ENABLE BIT(10) > +#define H_PULSE2_ENABLE BIT(12) > +#define V_PULSE0_ENABLE BIT(16) > +#define V_PULSE1_ENABLE BIT(18) > +#define V_PULSE2_ENABLE BIT(19) > +#define V_PULSE3_ENABLE BIT(20) [Severity: Low] Are the bit definitions for V_PULSE2_ENABLE and V_PULSE3_ENABLE correct here? The other enable bits follow a spacing pattern of +2 bits, like H_PULSE0 at 8, H_PULSE1 at 10, H_PULSE2 at 12, V_PULSE0 at 16, and V_PULSE1 at 18. However, V_PULSE2 and V_PULSE3 break this pattern by mapping to BIT(19) and BIT(20). If the pattern held, they would be BIT(20) and BIT(22). Is this an expected irregularity in the hardware layout, or could this be a typo? > +#define M0_ENABLE BIT(24) > +#define M1_ENABLE BIT(26) -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=1
