From: Biju Das <[email protected]> Hi All,
Enhance RZ/G2L MIPI DSI driver based on "Figure 34.5 Power on sequence", on section "34.4.2.1 Reset" of the RZ/G2L hardware manual Rev.1.50 May, 2025. As per the hardware manual, it is required to wait >= 1msec after deasserting the CMN_RSTB signal, and writing to DSI PHY timing registers and few LINK registers should be done before deasserting the CMN_RSTB. Biju Das (2): drm: renesas: rzg2l_mipi_dsi: Use fsleep() for 1ms delay in D-PHY init drm: renesas: rzg2l_mipi_dsi: Fix the power-on sequence .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 27 +++++++++++-------- 1 file changed, 16 insertions(+), 11 deletions(-) -- 2.43.0
