On Thu, Jul 17, 2025 at 04:28:46PM -0700, Jessica Zhang wrote: > From: Abhinav Kumar <quic_abhin...@quicinc.com> > > On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more, > the display port controller can support more than one pixel stream > (multi-stream transport). > > These chipsets can support up to 4 stream pixel clocks for display port > controller. To support MST on these platforms, add the appropriate > stream pixel clock bindings > > Since this mode is not supported on all chipsets, add exception > rules and min/max items to clearly mark which chipsets support > only SST mode (single stream) and which ones support MST. > > Note: On chipsets that do support MST, the number of streams supported > can vary between controllers. For example, SA8775P supports 4 MST > streams on mdss_dp0 but only 2 streams on mdss_dp1.
Then for this platform it should be oneOf: minItems: 6 / minItems: 8 > > In addition, many chipsets depend on the "sm8350-dp" compatibility > string but not all (ex. SM6350) support MST. Because of these reasons, > the min/maxItem for MST-supported platforms is a range of 5-8. Do we still consider them to be compatible? > > Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com> > Signed-off-by: Jessica Zhang <jessica.zh...@oss.qualcomm.com> > --- > .../bindings/display/msm/dp-controller.yaml | 36 > +++++++++++++++++++++- > .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++-- > .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++-- > 6 files changed, 59 insertions(+), 11 deletions(-) > -- With best wishes Dmitry
