On Thu, Jul 17, 2025 at 04:28:46PM -0700, Jessica Zhang wrote: > From: Abhinav Kumar <quic_abhin...@quicinc.com> > > On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more, > the display port controller can support more than one pixel stream > (multi-stream transport). > > These chipsets can support up to 4 stream pixel clocks for display port > controller. To support MST on these platforms, add the appropriate > stream pixel clock bindings > > Since this mode is not supported on all chipsets, add exception > rules and min/max items to clearly mark which chipsets support > only SST mode (single stream) and which ones support MST. > > Note: On chipsets that do support MST, the number of streams supported > can vary between controllers. For example, SA8775P supports 4 MST > streams on mdss_dp0 but only 2 streams on mdss_dp1. > > In addition, many chipsets depend on the "sm8350-dp" compatibility > string but not all (ex. SM6350) support MST. Because of these reasons, > the min/maxItem for MST-supported platforms is a range of 5-8. > > Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com> > Signed-off-by: Jessica Zhang <jessica.zh...@oss.qualcomm.com> > --- > .../bindings/display/msm/dp-controller.yaml | 36 > +++++++++++++++++++++- > .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++-- > .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++-- > 6 files changed, 59 insertions(+), 11 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > index d8d94f62c102..2893f097df82 100644 > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > @@ -58,20 +58,28 @@ properties: > maxItems: 1 > > clocks: > + minItems: 5 > items: > - description: AHB clock to enable register access > - description: Display Port AUX clock > - description: Display Port Link clock > - description: Link interface clock between DP and PHY > - - description: Display Port Pixel clock > + - description: Display Port stream 0 Pixel clock > + - description: Display Port stream 1 Pixel clock > + - description: Display Port stream 2 Pixel clock > + - description: Display Port stream 3 Pixel clock > > clock-names: > + minItems: 5 > items: > - const: core_iface > - const: core_aux > - const: ctrl_link > - const: ctrl_link_iface > - const: stream_pixel > + - const: stream_1_pixel > + - const: stream_2_pixel > + - const: stream_3_pixel > > phys: > maxItems: 1 > @@ -173,6 +181,32 @@ allOf: > required: > - "#sound-dai-cells" > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sa8775p-dp > + - qcom,sc7280-dp > + - qcom,sc8180x-dp > + - qcom,sc8280xp-dp > + - qcom,sc8280xp-edp > + - qcom,sm8150-dp > + - qcom,sm8350-dp > + - qcom,sm8650-dp > + - qcom,x1e80100-dp > + then: > + properties: > + clocks: > + minItems: 5 > + maxItems: 8
The hardware can't have variable list of clocks. Please describe the hardware here, specifying exact number of clocks to be used. > + > + else: > + properties: > + clocks: > + minItems: 5 > + maxItems: 5 > + > additionalProperties: false > > examples: -- With best wishes Dmitry
