[PATCH v1 5/5] ARM: tegra: add MIPI calibration binding for Tegra20/Tegra30

[Svyatoslav Ryhel]

Add MIPI calibration device node for Tegra20 and Tegra30.

Signed-off-by: Svyatoslav Ryhel <clamo...@gmail.com>
---
 arch/arm/boot/dts/nvidia/tegra20.dtsi | 14 ++++++++++++++
 arch/arm/boot/dts/nvidia/tegra30.dtsi | 18 ++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi 
b/arch/arm/boot/dts/nvidia/tegra20.dtsi
index 92d422f83ea4..521261045cc8 100644
--- a/arch/arm/boot/dts/nvidia/tegra20.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi
@@ -74,6 +74,16 @@ vi@54080000 {
                        status = "disabled";
                };
 
+               /* DSI MIPI calibration logic is a part of VI/CSI */
+               mipi: mipi@54080220 {
+                       compatible = "nvidia,tegra20-mipi";
+                       reg = <0x54080220 0x100>;
+                       clocks = <&tegra_car TEGRA20_CLK_VI>,
+                                <&tegra_car TEGRA20_CLK_CSI>;
+                       clock-names = "vi", "csi";
+                       #nvidia,mipi-calibrate-cells = <1>;
+               };
+
                epp@540c0000 {
                        compatible = "nvidia,tegra20-epp";
                        reg = <0x540c0000 0x00040000>;
@@ -219,9 +229,13 @@ dsi@54300000 {
                        clock-names = "dsi", "parent";
                        resets = <&tegra_car 48>;
                        reset-names = "dsi";
+                       nvidia,mipi-calibrate = <&mipi 0>;
                        power-domains = <&pd_core>;
                        operating-points-v2 = <&dsi_dvfs_opp_table>;
                        status = "disabled";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
        };
 
diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi 
b/arch/arm/boot/dts/nvidia/tegra30.dtsi
index 50b0446f43fc..c52ad3715505 100644
--- a/arch/arm/boot/dts/nvidia/tegra30.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi
@@ -164,6 +164,16 @@ vi@54080000 {
                        status = "disabled";
                };
 
+               /* DSI MIPI calibration logic is a part of VI/CSI */
+               mipi: mipi@54080220 {
+                       compatible = "nvidia,tegra30-mipi";
+                       reg = <0x54080220 0x100>;
+                       clocks = <&tegra_car TEGRA30_CLK_VI>,
+                                <&tegra_car TEGRA30_CLK_CSI>;
+                       clock-names = "vi", "csi";
+                       #nvidia,mipi-calibrate-cells = <1>;
+               };
+
                epp@540c0000 {
                        compatible = "nvidia,tegra30-epp";
                        reg = <0x540c0000 0x00040000>;
@@ -321,9 +331,13 @@ dsi@54300000 {
                        clock-names = "dsi", "parent";
                        resets = <&tegra_car 48>;
                        reset-names = "dsi";
+                       nvidia,mipi-calibrate = <&mipi 0>;
                        power-domains = <&pd_core>;
                        operating-points-v2 = <&dsia_dvfs_opp_table>;
                        status = "disabled";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                dsi@54400000 {
@@ -334,9 +348,13 @@ dsi@54400000 {
                        clock-names = "dsi", "parent";
                        resets = <&tegra_car 84>;
                        reset-names = "dsi";
+                       nvidia,mipi-calibrate = <&mipi 0>;
                        power-domains = <&pd_core>;
                        operating-points-v2 = <&dsib_dvfs_opp_table>;
                        status = "disabled";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
        };
 
-- 
2.48.1