Tegra20/Tegra30 are fully compatible with existing tegra DSI driver apart
clock configuration and MIPI calibration which are addressed by this patch.
Signed-off-by: Svyatoslav Ryhel <clamo...@gmail.com>
---
drivers/gpu/drm/tegra/drm.c | 2 ++
drivers/gpu/drm/tegra/dsi.c | 69 ++++++++++++++++++++++---------------
drivers/gpu/drm/tegra/dsi.h | 10 ++++++
3 files changed, 54 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 4596073fe28f..5d64cd57e764 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -1359,10 +1359,12 @@ static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops,
host1x_drm_suspend,
static const struct of_device_id host1x_drm_subdevs[] = {
{ .compatible = "nvidia,tegra20-dc", },
+ { .compatible = "nvidia,tegra20-dsi", },
{ .compatible = "nvidia,tegra20-hdmi", },
{ .compatible = "nvidia,tegra20-gr2d", },
{ .compatible = "nvidia,tegra20-gr3d", },
{ .compatible = "nvidia,tegra30-dc", },
+ { .compatible = "nvidia,tegra30-dsi", },
{ .compatible = "nvidia,tegra30-hdmi", },
{ .compatible = "nvidia,tegra30-gr2d", },
{ .compatible = "nvidia,tegra30-gr3d", },
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 3f91a24ebef2..85bcb8bee1ae 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -662,39 +662,48 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
{
u32 value;
- value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
- tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
+ /* Tegra20/30 uses DSIv0 while Tegra114+ uses DSIv1 */
+ if (of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra20-dsi") ||
+ of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra30-dsi")) {
+ value = DSI_PAD_CONTROL_LPUPADJ(0x1) |
DSI_PAD_CONTROL_LPDNADJ(0x1) |
+ DSI_PAD_CONTROL_PREEMP_EN(0x1) |
DSI_PAD_CONTROL_SLEWDNADJ(0x6) |
+ DSI_PAD_CONTROL_SLEWUPADJ(0x6) |
DSI_PAD_CONTROL_PDIO(0) |
+ DSI_PAD_CONTROL_PDIO_CLK(0) |
DSI_PAD_CONTROL_PULLDN_ENAB(0);
+ tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
+ } else {
+ /*
+ * XXX Is this still needed? The module reset is deasserted
right
+ * before this function is called.
+ */
+ tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
+ tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
+ tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
+ tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
+ tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
+
+ value = DSI_PAD_CONTROL_VS1_PULLDN(0) |
DSI_PAD_CONTROL_VS1_PDIO(0);
+ tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
+
+ value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
+ DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
+ DSI_PAD_OUT_CLK(0x0);
+ tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
+
+ value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3)
|
+ DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
+ tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
+ }
return 0;
}
static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
{
- u32 value;
int err;
- /*
- * XXX Is this still needed? The module reset is deasserted right
- * before this function is called.
- */
- tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
- tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
- tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
- tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
- tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
-
/* start calibration */
tegra_dsi_pad_enable(dsi);
- value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
- DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
- DSI_PAD_OUT_CLK(0x0);
- tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
-
- value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
- DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
- tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
-
err = tegra_mipi_start_calibration(dsi->mipi);
if (err < 0)
return err;
@@ -1615,7 +1624,7 @@ static int tegra_dsi_probe(struct platform_device *pdev)
goto remove;
}
- dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
+ dsi->clk_lp = devm_clk_get_optional(&pdev->dev, "lp");
if (IS_ERR(dsi->clk_lp)) {
err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp),
"cannot get low-power clock\n");
@@ -1636,10 +1645,14 @@ static int tegra_dsi_probe(struct platform_device *pdev)
goto remove;
}
- err = tegra_dsi_setup_clocks(dsi);
- if (err < 0) {
- dev_err(&pdev->dev, "cannot setup clocks\n");
- goto remove;
+ /* Tegra20/Tegra30 do not use DSI parent muxing */
+ if (!of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra20-dsi") &&
+ !of_device_is_compatible(dsi->dev->of_node, "nvidia,tegra30-dsi")) {
+ err = tegra_dsi_setup_clocks(dsi);
+ if (err < 0) {
+ dev_err(&pdev->dev, "cannot setup clocks\n");
+ return err;
+ }
}
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1709,6 +1722,8 @@ static const struct of_device_id tegra_dsi_of_match[] = {
{ .compatible = "nvidia,tegra132-dsi", },
{ .compatible = "nvidia,tegra124-dsi", },
{ .compatible = "nvidia,tegra114-dsi", },
+ { .compatible = "nvidia,tegra30-dsi", },
+ { .compatible = "nvidia,tegra20-dsi", },
{ },
};
MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.h
index f39594e65e97..d834ac0c47ab 100644
--- a/drivers/gpu/drm/tegra/dsi.h
+++ b/drivers/gpu/drm/tegra/dsi.h
@@ -95,6 +95,16 @@
#define DSI_TALLY_LRX(x) (((x) & 0xff) << 8)
#define DSI_TALLY_HTX(x) (((x) & 0xff) << 0)
#define DSI_PAD_CONTROL_0 0x4b
+/* Tegra20/Tegra30 */
+#define DSI_PAD_CONTROL_PULLDN_ENAB(x) (((x) & 0x1) << 28)
+#define DSI_PAD_CONTROL_SLEWUPADJ(x) (((x) & 0x7) << 24)
+#define DSI_PAD_CONTROL_SLEWDNADJ(x) (((x) & 0x7) << 20)
+#define DSI_PAD_CONTROL_PREEMP_EN(x) (((x) & 0x1) << 19)
+#define DSI_PAD_CONTROL_PDIO_CLK(x) (((x) & 0x1) << 18)
+#define DSI_PAD_CONTROL_PDIO(x) (((x) & 0x3) << 16)
+#define DSI_PAD_CONTROL_LPUPADJ(x) (((x) & 0x3) << 14)
+#define DSI_PAD_CONTROL_LPDNADJ(x) (((x) & 0x3) << 12)
+/* Tegra114+ */
#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
--
2.48.1
