Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.
Signed-off-by: Svyatoslav Ryhel <clamo...@gmail.com>
---
drivers/clk/tegra/clk-tegra20.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 2c58ce25af75..551ef0cf0c9a 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -802,9 +802,8 @@ static void __init tegra20_periph_clk_init(void)
clks[TEGRA20_CLK_MC] = clk;
/* dsi */
- clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
- 48, periph_clk_enb_refcnt);
- clk_register_clkdev(clk, NULL, "dsi");
+ clk = tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0, clk_base,
+ 0, 48, periph_clk_enb_refcnt);
clks[TEGRA20_CLK_DSI] = clk;
/* pex */
--
2.48.1
