So it can be shared for CP tests.

Reviewed-by: Ken Wang <Qingqing.Wang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 tests/amdgpu/basic_tests.c | 27 +++++++++++++++++----------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 7806be7..701ccf1 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -57,6 +57,7 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle 
context_handle,
                                       struct amdgpu_cs_request *ibs_request);
 static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
 static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
+static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type);

 CU_TestInfo basic_tests[] = {
        { "Query Info Test",  amdgpu_query_info_test },
@@ -955,7 +956,7 @@ static void amdgpu_command_submission_sdma_const_fill(void)
        amdgpu_command_submission_const_fill_helper(AMDGPU_HW_IP_DMA);
 }

-static void amdgpu_command_submission_sdma_copy_linear(void)
+static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type)
 {
        const int sdma_write_length = 1024;
        const int pm4_dw = 256;
@@ -1020,17 +1021,18 @@ static void 
amdgpu_command_submission_sdma_copy_linear(void)

                        /* fullfill PM4: test DMA copy linear */
                        i = j = 0;
-                       pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, 
SDMA_COPY_SUB_OPCODE_LINEAR, 0);
-                       pm4[i++] = sdma_write_length;
-                       pm4[i++] = 0;
-                       pm4[i++] = 0xffffffff & bo1_mc;
-                       pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
-                       pm4[i++] = 0xffffffff & bo2_mc;
-                       pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
-
+                       if (ip_type == AMDGPU_HW_IP_DMA) {
+                               pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, 
SDMA_COPY_SUB_OPCODE_LINEAR, 0);
+                               pm4[i++] = sdma_write_length;
+                               pm4[i++] = 0;
+                               pm4[i++] = 0xffffffff & bo1_mc;
+                               pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
+                               pm4[i++] = 0xffffffff & bo2_mc;
+                               pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
+                       }

                        amdgpu_test_exec_cs_helper(context_handle,
-                                                  AMDGPU_HW_IP_DMA, 0,
+                                                  ip_type, 0,
                                                   i, pm4,
                                                   2, resources,
                                                   ib_info, ibs_request);
@@ -1061,6 +1063,11 @@ static void 
amdgpu_command_submission_sdma_copy_linear(void)
        CU_ASSERT_EQUAL(r, 0);
 }

+static void amdgpu_command_submission_sdma_copy_linear(void)
+{
+       amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_DMA);
+}
+
 static void amdgpu_command_submission_sdma(void)
 {
        amdgpu_command_submission_sdma_write_linear();
-- 
2.5.0

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