So it can be shared for CP tests.

Reviewed-by: Ken Wang <Qingqing.Wang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 tests/amdgpu/basic_tests.c | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 1bcc835..5804503 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -55,6 +55,7 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle 
context_handle,
                                       int res_cnt, amdgpu_bo_handle *resources,
                                       struct amdgpu_cs_ib_info *ib_info,
                                       struct amdgpu_cs_request *ibs_request);
+static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);

 CU_TestInfo basic_tests[] = {
        { "Query Info Test",  amdgpu_query_info_test },
@@ -626,7 +627,7 @@ static void 
amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
        CU_ASSERT_EQUAL(r, 0);
 }

-static void amdgpu_command_submission_sdma_write_linear(void)
+static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
 {
        const int sdma_write_length = 128;
        const int pm4_dw = 256;
@@ -676,16 +677,18 @@ static void 
amdgpu_command_submission_sdma_write_linear(void)

                /* fullfill PM4: test DMA write-linear */
                i = j = 0;
-               pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
-                               SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
-               pm4[i++] = 0xffffffff & bo_mc;
-               pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
-               pm4[i++] = sdma_write_length;
-               while(j++ < sdma_write_length)
-                       pm4[i++] = 0xdeadbeaf;
+               if (ip_type == AMDGPU_HW_IP_DMA) {
+                       pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
+                                              SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
+                       pm4[i++] = 0xffffffff & bo_mc;
+                       pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
+                       pm4[i++] = sdma_write_length;
+                       while(j++ < sdma_write_length)
+                               pm4[i++] = 0xdeadbeaf;
+               }

                amdgpu_test_exec_cs_helper(context_handle,
-                                          AMDGPU_HW_IP_DMA, 0,
+                                          ip_type, 0,
                                           i, pm4,
                                           1, resources,
                                           ib_info, ibs_request);
@@ -712,6 +715,11 @@ static void 
amdgpu_command_submission_sdma_write_linear(void)
        CU_ASSERT_EQUAL(r, 0);
 }

+static void amdgpu_command_submission_sdma_write_linear(void)
+{
+       amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_DMA);
+}
+
 static void amdgpu_command_submission_sdma_const_fill(void)
 {
        const int sdma_write_length = 1024 * 1024;
-- 
2.5.0

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