George Nychis wrote:
I spend all of my time working with the single chain, and if I find bugs I can fix them. But I think you're the only ones using the dual chain... so your feedback is useful and I'd appreciate any help solving the problems. I don't really know Verilog, and our Verilog coder is at an internship right now ;)
The main reason I bring this up is that Brian and I were talking on IRC about the issue earlier, and agreed that a testbench for the FPGA timestamp would be useful in ensuring the timestamps are behaving properly... but I don't really know Verilog to do this easily ;) So if any of you know Verilog and want to collaborate on helping fix the issue, it would be appreciated.
- George _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
