On Wed, Dec 26, 2007 at 01:56:46AM -0800, Firas Abbas wrote:
> > I agree that the results do look better.  My concern is overflow when  
> > both I and Q are used.  If you can try all of these with max-strength  
> > signals on both I and Q at the same time, I would be more than happy to  
> > include the final results in the standard build of the FPGA. 
> 

> Actually we are using I & Q (The DDC out is complex as you know) and
> the FFT used in usrp_fft.py is complex FFT.
> However, If you prefer, I can repeat all the tests using DBSRX
> board, or please suggest what tests you would like me to do.

I believe that Matt was referring to using max-strength I & Q inputs
to the Basic Rx along with an Rx mux setting that routes both ADC
outputs into the same DDC.  (The default config with the Basic Rx
feeds a constant zero into the Q DDC input).

Eric


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