Hi Don Good analysis.
>>Don Ward <[EMAIL PROTECTED]> wrote: >> >>I think we could quickly double the processing gain (and gain 6 dB >>S/N and >>dynamic range at higher decimation rates) by either shifting >>by 4 bits >>before the CORDIC stage or eliminating the divide by 2 at >>the end of the >>CORDIC stage. Can you modify the FPGA quickly and send me the RBF file?. I want to make use from the measuring equipments I have currently to test the modifications before I return it back. Regards, Firas A.
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