(This is migrated from edk2-platforms)
The current (and future) RISC-V platforms share a lot of PlatformPei
code that does not need to be duplicated. If we see that they need to
have different behavior in the future, we can add platform specific
libraires for that specific code.
The upcoming RiscvVirt is only 1205 lines with this patch.
Still way too much. Hopefully MinPlatform will help.
26 ./RiscvVirt.dec
13 ./RiscvVirt.uni
12 ./RiscvVirtPkgExtra.uni
78 ./VarStore.fdf.inc
66 ./RiscvVirt.fdf.inc
654 ./RiscvVirt.dsc
356 ./RiscvVirt.fdf
1205 total
Cc: Abner Chang <abner.ch...@hpe.com>
Cc: Sunil V L <suni...@ventanamicro.com>
Reviewed-by: Abner Chang <abner.ch...@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schae...@hpe.com>
---
.../Universal/Pei/PlatformPei/PlatformPei.inf | 74 +++++
.../Universal/Pei/PlatformPei/Platform.h | 86 +++++
.../Universal/Pei/PlatformPei/Fv.c | 51 +++
.../Universal/Pei/PlatformPei/MemDetect.c | 81 +++++
.../Universal/Pei/PlatformPei/Platform.c | 314 ++++++++++++++++++
5 files changed, 606 insertions(+)
create mode 100644
Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
create mode 100644
Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
create mode 100644
Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
create mode 100644
Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
diff --git
a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
new file mode 100644
index 0000000000..e7f5eef630
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
@@ -0,0 +1,74 @@
+## @file
+# Platform PEI driver
+#
+# This module provides platform specific function to detect boot mode.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformPei
+ FILE_GUID = 5592FC16-8FEF-4DE3-A6CF-6C59081E4EB7
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializePlatform
+
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Fv.c
+ MemDetect.c
+ Platform.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+ Silicon/SiFive/SiFive.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Guids]
+ gEfiMemoryTypeInformationGuid
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ IoLib
+ PciLib
+ PeiResourcePublicationLib
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ PeimEntryPoint
+ PcdLib
+ SiliconSiFiveU5MCCoreplexInfoLib
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize
+ gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported
+
+[Ppis]
+ gEfiPeiMasterBootModePpiGuid
+
+[Depex]
+ TRUE
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
new file mode 100644
index 0000000000..c2cdd6d75b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
@@ -0,0 +1,86 @@
+/** @file
+ Platform PEI module include file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_PEI_H_INCLUDED_
+#define PLATFORM_PEI_H_INCLUDED_
+
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddIoMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddUntestedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddReservedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddUntestedMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddressWidthInitialization (
+ VOID
+ );
+
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ );
+
+UINT32
+GetSystemMemorySizeBelow4gb (
+ VOID
+ );
+
+VOID
+InitializeRamRegions (
+ VOID
+ );
+
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ );
+
+EFI_STATUS
+InitializeXen (
+ VOID
+ );
+
+#endif // _PLATFORM_PEI_H_INCLUDED_
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
new file mode 100644
index 0000000000..060d66238d
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
@@ -0,0 +1,51 @@
+/** @file
+ Build FV related hobs for platform.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PiPei.h"
+#include "Platform.h"
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+
+/**
+ Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+ and DXE know about them.
+
+ @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.
+
+**/
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
+ //
+ // Let DXE know about the DXE FV
+ //
+ BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
+ DEBUG ((DEBUG_INFO, "Platform builds DXE FV at %x, size %x.\n",
+ PcdGet32 (PcdRiscVDxeFvBase),
+ PcdGet32 (PcdRiscVDxeFvSize)));
+
+ //
+ // Let PEI know about the DXE FV so it can find the DXE Core
+ //
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
+ PcdGet32 (PcdRiscVDxeFvSize),
+ NULL,
+ NULL
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
new file mode 100644
index 0000000000..c15d6bb5d4
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
@@ -0,0 +1,81 @@
+/**@file
+ Memory Detection for Virtual Machines.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+Module Name:
+
+ MemDetect.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/ResourcePublicationLib.h>
+
+#include "Platform.h"
+
+
+/**
+ Publish PEI core memory
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS MemoryBase;
+ UINT64 MemorySize;
+
+ //
+ // TODO: This value should come from platform
+ // configuration or the memory sizing code.
+ //
+ MemoryBase = 0x80000000UL + 0x1000000UL;
+ MemorySize = 0x40000000UL - 0x1000000UL; //1GB - 16MB
+
+ DEBUG((DEBUG_INFO, "%a: MemoryBase:0x%x MemorySize:%x\n", __FUNCTION__,
MemoryBase, MemorySize));
+
+ //
+ // Publish this memory to the PEI Core
+ //
+ Status = PublishSystemMemory(MemoryBase, MemorySize);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Publish system RAM and reserve memory regions
+
+**/
+VOID
+InitializeRamRegions (
+ VOID
+ )
+{
+ //
+ // TODO: This value should come from platform
+ // configuration or the memory sizing code.
+ //
+ AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL);
+}
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
new file mode 100644
index 0000000000..24192c692b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
@@ -0,0 +1,314 @@
+/**@file
+ Platform PEI driver
+
+ Copyright (c) 2019-2021, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2011, Andrei Warkentin <andr...@motorola.com>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ResourcePublicationLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Ppi/MasterBootMode.h>
+#include <IndustryStandard/Pci22.h>
+
+#include <SiFiveU5MCCoreplex.h>
+
+#include "Platform.h"
+
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIMemoryNVS, 0x004 },
+ { EfiACPIReclaimMemory, 0x008 },
+ { EfiReservedMemoryType, 0x004 },
+ { EfiRuntimeServicesData, 0x024 },
+ { EfiRuntimeServicesCode, 0x030 },
+ { EfiBootServicesCode, 0x180 },
+ { EfiBootServicesData, 0xF00 },
+ { EfiMaxMemoryType, 0x000 }
+};
+
+
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiMasterBootModePpiGuid,
+ NULL
+ }
+};
+
+STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddReservedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_RESERVED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddIoMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+
+VOID
+AddMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+
+VOID
+AddMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+
+VOID
+AddUntestedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddUntestedMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit -
MemoryBase));
+}
+
+VOID
+AddPciResource (
+ VOID
+ )
+{
+ //
+ // Platform-specific
+ //
+}
+
+VOID
+MemMapInitialization (
+ VOID
+ )
+{
+ //
+ // Create Memory Type Information HOB
+ //
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ mDefaultMemoryTypeInformation,
+ sizeof(mDefaultMemoryTypeInformation)
+ );
+
+ //
+ // Add PCI IO Port space available for PCI resource allocations.
+ //
+ AddPciResource ();
+}
+
+VOID
+MiscInitialization (
+ VOID
+ )
+{
+ //
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
+ // S3 resume as well, so we build it unconditionally.)
+ //
+ // TODO: Determine this dynamically from the platform
+ // setting or the HART configuration.
+ //
+ BuildCpuHob (48, 32);
+}
+
+/**
+ Check if system returns from S3.
+
+ @return BOOLEAN TRUE, system returned from S3
+ FALSE, system is not returned from S3
+
+**/
+BOOLEAN
+CheckResumeFromS3 (
+ VOID
+ )
+{
+ //
+ //Platform implementation-specific
+ //
+ return FALSE;
+}
+
+
+VOID
+BootModeInitialization (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ if (CheckResumeFromS3 () == TRUE) {
+ DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "This is normal boot\n"));
+ }
+ Status = PeiServicesSetBootMode (mBootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PeiServicesInstallPpi (mPpiBootMode);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Build processor information for U54 Coreplex processor.
+
+ @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildCoreInformationHob (
+ VOID
+)
+{
+ EFI_STATUS Status;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;
+
+ // TODO: Create SMBIOS libs for non-U540 platforms
+ Status = CreateU5MCCoreplexProcessorSpecificDataHob (0);
+ if (EFI_ERROR (Status)) {
+ ASSERT(FALSE);
+ }
+ Status = CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);
+ if (EFI_ERROR (Status)) {
+ ASSERT(FALSE);
+ }
+
+ DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n",
SmbiosHobPtr));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Perform Platform PEI initialization.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializePlatform (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
+
+ BootModeInitialization ();
+ DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n"));
+ PublishPeiMemory ();
+ DEBUG ((DEBUG_INFO, "PEI memory published.\n"));
+ InitializeRamRegions ();
+ DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n"));
+
+ if (mBootMode != BOOT_ON_S3_RESUME) {
+ PeiFvInitialization ();
+ MemMapInitialization ();
+ }
+
+ MiscInitialization ();
+ Status = BuildCoreInformationHob ();
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n"));
+ ASSERT(FALSE);
+ }
+ return EFI_SUCCESS;
+}
--
2.31.1
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