(This is migrated from edk2-platforms:Platform/RISC-V)
Add RISC-V platform package.
Signed-off-by: Abner Chang <abner.ch...@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schae...@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.c...@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Gilbert Chen <gilbert.c...@hpe.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 77 +++++++++++++
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 81 ++++++++++++++
Platform/RISC-V/PlatformPkg/Readme.md | 104 ++++++++++++++++++
.../RISC-V/PlatformPkg/RiscVPlatformPkg.uni | 15 +++
.../PlatformPkg/RiscVPlatformPkgExtra.uni | 12 ++
5 files changed, 289 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
create mode 100644 Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
create mode 100644 Platform/RISC-V/PlatformPkg/Readme.md
create mode 100644 Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni
create mode 100644 Platform/RISC-V/PlatformPkg/RiscVPlatformPkgExtra.uni
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
new file mode 100644
index 0000000000..48aeb97431
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -0,0 +1,77 @@
+## @file RiscVPlatformPkg.dec
+# This Package provides UEFI RISC-V platform modules and libraries.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = RiscVPlatformPkg
+ PACKAGE_UNI_FILE = RiscVPlatformPkg.uni
+ PACKAGE_GUID = B51DBDBB-B43D-4D45-8CDD-1D6D1C691003
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+ Include
+
+[LibraryClasses]
+
FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProcessorSpecificLib.h
+
RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryInitLib.h
+
+[Guids]
+ gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6,
0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}}
+
+[PcdsFixedAtBuild]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|0x0|UINT32|0x00001000
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize|0x0|UINT32|0x00001001
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|0x0|UINT32|0x00001002
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005
+
+#
+# Definition of EFI Variable region
+#
+
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001010
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011
+
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001012
+
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001013
+
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001014
+
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001015
+#
+# Firmware region which is protected by PMP.
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022
+#
+# Definition of RISC-V Hart
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024
+#
+# The bootable hart core number, which is incorporate with OpenSBI platform
hart_index2id value.
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x00001025
+#
+# Definitions for OpenSbi
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001100
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize|0|UINT32|0x00001101
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize|0|UINT32|0x00001102
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x00001103
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001104
+
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPeiCorePrivilegeMode|0|UINT32|0x00001105
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001006
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RiscVPlatformPkgExtra.uni
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
new file mode 100644
index 0000000000..092717d2ef
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -0,0 +1,81 @@
+#/** @file
+# RISC-V platform package.
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+################################################################################
+#
+# Defines Section
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = RiscVPlatform
+ PLATFORM_GUID = 840A9576-5869-491E-9210-89769DED4650
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001c
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = RISCV64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+[BuildOptions]
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable
+!endif
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT
+
+[LibraryClasses.common]
+
RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+ RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
+
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
+
RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+[LibraryClasses.common.PEIM]
+
FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+
+[LibraryClasses.common.SEC]
+
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+
PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+
+[Components.common]
+
Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+
Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
+
Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+
Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
+
Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
+
Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
+
+[Components.common.SEC]
+ Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+
diff --git a/Platform/RISC-V/PlatformPkg/Readme.md
b/Platform/RISC-V/PlatformPkg/Readme.md
new file mode 100644
index 0000000000..2632ebeb28
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Readme.md
@@ -0,0 +1,104 @@
+# Introduction
+
+## EDK2 RISC-V Platform Packages
+RISC-V platform package provides the generic and common modules for RISC-V
+platforms. RISC-V platform package could include RiscPlatformPkg.dec to
+use the common drivers, libraries, definitions, PCDs and etc. for the
+platform development.
+
+There are two packages to support RISC-V:
+- `edk2-platforms/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec`
+- `edk2-platforms/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec`
+
+`RiscVPlatformPkg` provides SEC phase and NULL libs.
+`RiscVProcessorPkg` provides many libraries, PEIMs and DXE drivers.
+
+### Download the sources ###
+```
+git clone https://github.com/tianocore/edk2.git
+
+git clone https://github.com/changab/edk2-platforms.git
+# Check out branch: riscv-smode-lib
+```
+
+To build it, you have to follow the regular steps for EDK2 and additionally set
+an environmen variable to point to your RISC-V toolchain installation,
+including the binary prefixes:
+
+```
+export
GCC5_RISCV64_PREFIX=/riscv-gnu-toolchain-binaries/bin/riscv64-unknown-elf-
+```
+
+Then you can build the image for the SiFive HifiveUnleashed platform:
+
+```
+build -a RISCV64 -t GCC5 -p
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+```
+
+### EDK2 project
+All changes in edk2 are upstream, however, most of the RISC-V code is in
+edk2-platforms. Therefore you have to check out the branch `riscv-smode-lib` on
+`github.com/changab/edk2-platforms`.
+
+The build architecture which is supported and verified so far is `RISCV64`.
+The latest master of the RISC-V toolchain
https://github.com/riscv/riscv-gnu-toolchain
+should work but the latest verified commit is
`b468107e701433e1caca3dbc8aef8d40`.
+Toolchain tag is "GCC5" declared in `tools_def.txt`
+
+## RISC-V Platform PCD settings
+### EDK2 Firmware Volume Settings
+EDK2 Firmware volume related PCDs which declared in platform FDF file.
+
+| **PCD name** |**Usage**|
+|--------------|---------|
+|PcdRiscVSecFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVSecFvSize| The size of SEC Firmware Volume|
+|PcdRiscVPeiFvBase| The base address of PEI Firmware Volume|
+|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|
+|PcdRiscVDxeFvBase| The base address of DXE Firmware Volume|
+|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|
+
+### EDK2 EFI Variable Region Settings
+The PCD settings regard to EFI Variable
+
+| **PCD name** |**Usage**|
+|--------------|---------|
+|PcdVariableFdBaseAddress| The EFI variable firmware device base address|
+|PcdVariableFdSize| The EFI variable firmware device size|
+|PcdVariableFdBlockSize| The block size of EFI variable firmware device|
+|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within
firmware device|
+|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable
fault tolerance worksapce (FTW) within firmware device|
+|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare
FTW within firmware device|
+
+### RISC-V Physical Memory Protection (PMP) Region Settings
+Below PCDs could be set in platform FDF file.
+
+| **PCD name** |**Usage**|
+|--------------|---------|
+|PcdFwStartAddress| The starting address of firmware region to protected by
PMP|
+|PcdFwEndAddress| The ending address of firmware region to protected by PMP|
+
+### RISC-V Processor HART Settings
+
+| **PCD name** |**Usage**|
+|--------------|---------|
+|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation
specific|
+|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot
system to OS|
+
+### RISC-V OpenSBI Settings
+
+| **PCD name** |**Usage**|
+|--------------|---------|
+|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V
HARTs|
+|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-V
HARTs|
+|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for
booting system use OpenSBI|
+|PcdTemporaryRamBase| The base address of temporary memory for PEI phase|
+|PcdTemporaryRamSize| The temporary memory size for PEI phase|
+
+## Supported Operating Systems
+Only support to boot to EFI Shell so far.
+
+Porting GRUB2 and Linux EFISTUB is in progress.
+
+## Known Issues and Limitations
+Only RISC-V RV64 is verified.
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni
b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni
new file mode 100644
index 0000000000..deb91fa10c
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni
@@ -0,0 +1,15 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI
compatible RISC-V platform modules and libraries"
+
+#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides
UEFI compatible RISC-V platform modules and libraries."
+
+
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkgExtra.uni
b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkgExtra.uni
new file mode 100644
index 0000000000..493f5f42fe
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkgExtra.uni
@@ -0,0 +1,12 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_PACKAGE_NAME
+#language en-US
+"RISC-V platform package"
--
2.31.1
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