On October 12, 2021 6:16 PM, Gerd Hoffman wrote:
> Hi,
>
> > + do {
> > + AsmCpuid (0, &LargestEax, &Ebx, &Ecx, &Edx);
>
> Use ConfidentialComputing PCD ?
BaseXApicX2ApicLib (LocalApicLib) is included by the drivers/libs not only in
DXE phase, but also in SEC/PEI. For example, SecPeiCpuExceptionHandlerLib is
included in SEC/PEI_CORE/PEIM. In SEC phase ConfidentialComputing PCD has not
been set. So it cannot be used in SEC phase to determine if it is TDX guest or
not.
That's why CPUID is used in BaseXApicX2ApicLib so that it works in SEC/PEI/DXE
phases.
>
> > +BOOLEAN
> > +EFIAPI
> > +AccessMsrNative (
>
> I'd suggest to reverse the logic, i.e. have a AccessMsrTdxCall() which returns
> true in case (a) tdx is active and (b) the msr is not on the white list for
> native
> access ...
>
> > +{
> > + UINT64 Val;
> > + UINT64 Status;
> > + if (!AccessMsrNative (MsrIndex) && BaseXApicIsTdxGuest ()) {
>
> ... the just use "if (AccessMsrTdxCall(MsrIndex)) { ..." here.
>
Ok, It will be updated in the next version.
> Beside that: Are the apic msr registers the only ones which can be accessed
> directly?
TDX:
https://software.intel.com/content/dam/develop/external/us/en/documents/tdx-module-1.0-public-spec-v0.931.pdf
Section 10.7 MSR Handling
Section 18.1 Table 18.2 MSR Virtualization
X2APIC MSR Registers which can be accessed natively is in above table.
>
Thanks!
Min
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