From: Antoine Coeur <co...@gmx.fr>
Fix few typos in comments and documentation.
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Laszlo Ersek <ler...@redhat.com>
Signed-off-by: Antoine Coeur <co...@gmx.fr>
Reviewed-by: Philippe Mathieu-Daude <phi...@redhat.com>
Reviewed-by: Laszlo Ersek <ler...@redhat.com>
Reviewed-by: Eric Dong <eric.d...@intel.com>
Signed-off-by: Philippe Mathieu-Daude <phi...@redhat.com>
---
UefiCpuPkg/CpuDxe/CpuDxe.h | 2 +-
UefiCpuPkg/CpuDxe/CpuGdt.h | 2 +-
UefiCpuPkg/CpuDxe/CpuMp.h | 4 ++--
UefiCpuPkg/CpuDxe/CpuPageTable.h | 2 +-
UefiCpuPkg/CpuDxe/CpuDxe.c | 8 ++++----
UefiCpuPkg/CpuDxe/CpuGdt.c | 2 +-
UefiCpuPkg/CpuDxe/CpuMp.c | 4 ++--
UefiCpuPkg/CpuDxe/CpuPageTable.c | 6 +++---
8 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/CpuDxe.h
index a6762f1a0b78..9299eaa63d8a 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.h
@@ -208,7 +208,7 @@ CpuGetTimerValue (
);
/**
- Set memory cacheability attributes for given range of memeory.
+ Set memory cacheability attributes for given range of memory.
@param This Protocol instance structure
@param BaseAddress Specifies the start address of the
diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h
index e5c36f37b96a..3a0210b2f172 100644
--- a/UefiCpuPkg/CpuDxe/CpuGdt.h
+++ b/UefiCpuPkg/CpuDxe/CpuGdt.h
@@ -1,5 +1,5 @@
/** @file
- C based implemention of IA32 interrupt handling only
+ C based implementation of IA32 interrupt handling only
requiring a minimal assembly interrupt entry point.
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h
index e7e115fc8f3d..4ee171d8c491 100644
--- a/UefiCpuPkg/CpuDxe/CpuMp.h
+++ b/UefiCpuPkg/CpuDxe/CpuMp.h
@@ -147,7 +147,7 @@ GetProcessorInfo (
and releases the BSP to continue with other tasks.
-# The caller can use the CheckEvent() and WaitForEvent() services to check
the state of the WaitEvent created in step 1.
- -# When the APs complete their task or TimeoutInMicroSecondss expires, the
MP
+ -# When the APs complete their task or TimeoutInMicroSeconds expires, the
MP
Service signals WaitEvent by calling the EFI SignalEvent() function. If
FailedCpuList is not NULL, its content is available when WaitEvent is
signaled. If all APs returned from Procedure prior to the timeout, then
@@ -254,7 +254,7 @@ StartupAllAPs (
This function is used to dispatch one enabled AP to the function specified by
Procedure passing in the argument specified by ProcedureArgument. If
WaitEvent
is NULL, execution is in blocking mode. The BSP waits until the AP finishes
or
- TimeoutInMicroSecondss expires. Otherwise, execution is in non-blocking mode.
+ TimeoutInMicroSeconds expires. Otherwise, execution is in non-blocking mode.
BSP proceeds to the next task without waiting for the AP. If a non-blocking
mode
is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled,
then EFI_UNSUPPORTED must be returned.
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.h b/UefiCpuPkg/CpuDxe/CpuPageTable.h
index bad6784bcb51..0b2a02a2be5c 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.h
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.h
@@ -78,7 +78,7 @@ VOID *
Caller should make sure BaseAddress and Length is at page boundary.
- Caller need guarentee the TPL <= TPL_NOTIFY, if there is split page request.
+ Caller need guarantee the TPL <= TPL_NOTIFY, if there is split page request.
@param PagingContext The paging context. NULL means get page table from
current CPU context.
@param BaseAddress The physical address that is the start address of
a memory region.
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c
index 7d7270e10b4a..a571fc3b1750 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.c
@@ -393,7 +393,7 @@ CpuSetMemoryAttributes (
//
// If this function is called because GCD SetMemorySpaceAttributes () is
called
- // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory
+ // by RefreshGcdMemoryAttributes (), then we are just synchronizing GCD
memory
// map with MTRR values. So there is no need to modify MTRRs, just return
immediately
// to avoid unnecessary computing.
//
@@ -456,7 +456,7 @@ CpuSetMemoryAttributes (
CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress);
if (CurrentCacheType != CacheType) {
//
- // call MTRR libary function
+ // call MTRR library function
//
Status = MtrrSetMemoryAttribute (
BaseAddress,
@@ -831,7 +831,7 @@ RefreshMemoryAttributesFromMtrr (
Attributes = CurrentAttributes;
} else {
//
- // If fixed MTRR attribute changed, then set memory attribute for
previous atrribute
+ // If fixed MTRR attribute changed, then set memory attribute for
previous attribute
//
if (CurrentAttributes != Attributes) {
SetGcdMemorySpaceAttributes (
@@ -1045,7 +1045,7 @@ IntersectMemoryDescriptor (
@param Length Length of the MMIO space.
@param Capabilities Capabilities of the MMIO space.
- @retval EFI_SUCCES The MMIO space was added successfully.
+ @retval EFI_SUCCESS The MMIO space was added successfully.
**/
EFI_STATUS
AddMemoryMappedIoSpace (
diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c
index 87fd6955f24b..64efadeba601 100644
--- a/UefiCpuPkg/CpuDxe/CpuGdt.c
+++ b/UefiCpuPkg/CpuDxe/CpuGdt.c
@@ -1,5 +1,5 @@
/** @file
- C based implemention of IA32 interrupt handling only
+ C based implementation of IA32 interrupt handling only
requiring a minimal assembly interrupt entry point.
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
index de6c6a5c330c..60ede38df4fc 100644
--- a/UefiCpuPkg/CpuDxe/CpuMp.c
+++ b/UefiCpuPkg/CpuDxe/CpuMp.c
@@ -164,7 +164,7 @@ GetProcessorInfo (
and releases the BSP to continue with other tasks.
-# The caller can use the CheckEvent() and WaitForEvent() services to check
the state of the WaitEvent created in step 1.
- -# When the APs complete their task or TimeoutInMicroSecondss expires, the
MP
+ -# When the APs complete their task or TimeoutInMicroSeconds expires, the
MP
Service signals WaitEvent by calling the EFI SignalEvent() function. If
FailedCpuList is not NULL, its content is available when WaitEvent is
signaled. If all APs returned from Procedure prior to the timeout, then
@@ -281,7 +281,7 @@ StartupAllAPs (
This function is used to dispatch one enabled AP to the function specified by
Procedure passing in the argument specified by ProcedureArgument. If
WaitEvent
is NULL, execution is in blocking mode. The BSP waits until the AP finishes
or
- TimeoutInMicroSecondss expires. Otherwise, execution is in non-blocking mode.
+ TimeoutInMicroSeconds expires. Otherwise, execution is in non-blocking mode.
BSP proceeds to the next task without waiting for the AP. If a non-blocking
mode
is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled,
then EFI_UNSUPPORTED must be returned.
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index cb121771425a..0a02cb3f6b7e 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -776,7 +776,7 @@ ConvertMemoryPageAttributes (
}
//
- // Below logic is to check 2M/4K page to make sure we donot waist memory.
+ // Below logic is to check 2M/4K page to make sure we do not waste memory.
//
Status = EFI_SUCCESS;
while (Length != 0) {
@@ -838,7 +838,7 @@ Done:
Caller should make sure BaseAddress and Length is at page boundary.
- Caller need guarentee the TPL <= TPL_NOTIFY, if there is split page request.
+ Caller need guarantee the TPL <= TPL_NOTIFY, if there is split page request.
@param[in] PagingContext The paging context. NULL means get page table
from current CPU context.
@param[in] BaseAddress The physical address that is the start address
of a memory region.
@@ -969,7 +969,7 @@ RefreshGcdMemoryAttributesFromPaging (
);
if (EFI_ERROR (Status)) {
//
- // If we cannot udpate the capabilities, we cannot update its
+ // If we cannot update the capabilities, we cannot update its
// attributes either. So just simply skip current block of memory.
//
DEBUG ((
--
2.21.0
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